AD9524BCPZ datasheet(54/56 Pages) AD

Part #	AD9524BCPZ

Description	Jitter Cleaner and Clock Generator

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AD9524

Data Sheet

Rev. F | Page 54 of 56

Table 57. Power-Down Control

Address

Bits

Bit Name

Description

0x233

[7:3]

Reserved

Reserved.

2

PLL1 power-down

1: power-down (default).

0: normal operation.

1

PLL2 power-down

1: power-down (default).

0: normal operation.

0

Distribution power-

down

Powers down the distribution.

1: power-down (default).

0: normal operation.

Table 58. Update All Registers

Address

Bits

Bit Name

Description

0x234

[7:1]

Reserved

Reserved.

0

IO_Update

This bit must be set to 1 to transfer the contents of the buffer registers into the active registers,

which happens on the next SCLK rising edge. This bit is self clearing; that is, it does not have to

be set back to 0.

1 (self clearing): update all active registers to the contents of the buffer registers.

EEPROM Buffer (Address 0xA00 to Address 0xA16)

Table 59. EEPROM Buffer Segment

Address

Bits

Bit Name

Description

0xA00

to

0xA16

[7:0]

EEPROM Buffer

Segment Register 1 to

EEPROM Buffer

Segment Register 23

The EEPROM buffer segment section stores the starting address and number of bytes that are to

be stored and read back to and from the EEPROM. Because the register space is noncontiguous,

the EEPROM controller needs to know the starting address and number of bytes in the register

space to store and retrieve from the EEPROM. In addition, there are special instructions for the

EEPROM controller: operational codes (that is, IO_Update and end-of-data) that are also stored

in the EEPROM buffer segment. The on-chip default setting of the EEPROM buffer segment

registers is designed such that all registers are transferred to/from the EEPROM, and an

IO_Update is issued after the transfer (see the Programming the EEPROM Buffer Segment section).

EEPROM Control (Address 0xB00 to Address 0xB03)

Table 60. Status_EEPROM

Address

Bits

Bit Name

Description

0xB00

[7:1]

Reserved

Reserved.

0

Status_EEPROM

(read only)

This read-only bit indicates the status of the data transferred between the EEPROM and the

buffer register bank during the writing and reading of the EEPROM. This signal is also available

at the STATUS0 pin when Register 0x232, Bit 4 is set.

0: data transfer is complete.

1: data transfer is not complete.

Table 61. EEPROM Error Checking Readback

Address

Bits

Bit Name

Description

0xB01

[7:1]

Reserved

Reserved.

0

EEPROM data error

(read only)

This read-only bit indicates an error during the data transfer between the EEPROM and the buffer.

0: no error; data is correct.

1: incorrect data detected.

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