AD9524BCPZ datasheet(52/56 Pages) AD

Part #	AD9524BCPZ

Description	Jitter Cleaner and Clock Generator

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AD9524

Data Sheet

Rev. F | Page 52 of 56

Address

Bits

Bit Name

Description

0x22D

[7:4]

Reserved

3

Holdover active

1: holdover is active (both references are missing)

0: normal operation

2

Selected reference

(in auto mode)

Selected reference (applies only when the device automatically selects the reference;

for example, not in manual control mode)

1: REFB

0: REFA

1

Reserved

0

VCO calibration in progress

1: VCO calibration in progress

0: VCO calibration not in progress

Other (Address 0x230 to Address 0x234)

Table 56. Status Signals

Address

Bits

Bit Name

Description

0x230

[7:6]

Reserved

[5:0]

Status Monitor 0 control

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Muxout

0

GND

0

1

PLL1 and PLL2 locked

0

1

0

PLL1 locked

0

1

PLL2 locked

0

1

0

Both references are missing (REFA and REFB)

0

1

0

1

Both references are missing and PLL2 is locked

0

1

0

REFB selected (applies only to auto select mode)

0

1

REFA is OK

0

1

0

REFB is OK

0

1

0

1

REF_TEST is OK

0

1

0

1

0

VCXO is OK

0

1

0

1

PLL1 feedback is OK

0

1

0

PLL2 reference clock is OK

0

1

0

1

Reserved

0

1

0

REFA and REFB are OK

0

1

All clocks are OK (except REF_TEST)

0

1

0

PLL1 feedback is divide-by-2

0

1

0

1

PLL1 PFD down divide-by-2

0

1

0

1

0

PLL1 REF divide-by-2

0

1

0

1

PLL1 PFD up divide-by-2

0

1

0

1

0

GND

0

1

0

1

0

1

GND

0

1

0

1

0

GND

0

1

0

1

GND

Note that all bit combinations after 010111 are reserved.

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