AD9524BCPZ datasheet(45/56 Pages) AD

Part #	AD9524BCPZ

Description	Jitter Cleaner and Clock Generator

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Data Sheet

AD9524

Rev. F | Page 45 of 56

Table 41. PLL1 Input Receiver Control

Address

Bits

Bit Name

Description

0x01A

7

REF_TEST input receiver enable

1: enabled.

0: disabled (default).

6

REFB differential receiver enable

1: differential receiver mode.

0: single-ended receiver mode (also depends on Register 0x01B, Bit 1) (default).

5

REFA differential receiver enable

1: differential receiver mode.

0: single-ended receiver mode (also depends on Register 0x01B, Bit 0) (default).

4

REFB receiver enable

REFB receiver power-down control mode only when Bit 2 = 1.

1: enable REFB receiver.

0: power-down (default).

3

REFA receiver enable

REFA receiver power-down control mode only when Bit 2 = 1.

1: enable REFA receiver.

0: power-down (default).

2

Input REFA and REFB receiver

power-down control enable

Enables power-down control of the input receivers, REFA and REFB.

1: power-down control enabled.

0: both receivers enabled (default).

1

OSC_IN single-ended receiver

mode enable (CMOS mode)

Selects which single-ended input pin is enabled when in the single-ended receiver

mode (Register 0x01A, Bit 0 = 0).

1: negative receiver from oscillator input (OSC_IN pin) selected.

0: positive receiver from oscillator input (OSC_IN pin) selected (default).

0

OSC_IN differential receiver mode

enable

1: differential receiver mode.

0: single-ended receiver mode (also depends on Bit 1) (default).

Table 42. REF_TEST, REFA, REFB, and ZD_IN Control

Address

Bits

Bit Name

Description

0x01B

[7:6]

Reserved

0: reserved (default).

5

Zero delay mode

Selects the zero delay mode used (via the ZD_IN pin) when Register 0x01B, Bit 4 = 0.

Otherwise, this bit is ignored.

1: internal zero delay mode. The zero delay receiver is powered down. The internal

zero delay path from Distribution Divider Channel 0 is used.

0: external zero delay mode. The ZD_IN receiver is enabled.

4

OSC_IN signal feedback for PLL1

Controls the input PLL feedback path, local feedback from the OSC_IN receiver or

zero delay mode.

1: OSC_IN receiver input used for the input PLL feedback (non-zero delay mode).

0: zero delay mode enabled (also depends on Register 0x01B, Bit 4 to select the

zero delay path.

3

ZD_IN single-ended receiver

mode enable (CMOS mode)

Selects which single-ended input pin is enabled when in the single-ended receiver

mode (Register 0x01B, Bit 2 = 0).

1: ZD_IN pin enabled.

0: ZD_IN pin enabled.

2

ZD_IN differential receiver mode

enable

1: differential receiver mode.

0: single-ended receiver mode (also depends on Register 0x01B, Bit 3).

1

REFB single-ended receiver mode

enable (CMOS mode)

Selects which single-ended input pin is enabled when in single-ended receiver mode

(Register 0x01A, Bit 6 = 0).

1: REFB pin enabled.

0: REFB pin enabled.

0

REFA single-ended receiver mode

enable (CMOS mode)

Selects which single-ended input pin is enabled when in single-ended receiver mode

(Register 0x01A, Bit 5 = 0).

1: REFA pin enabled.

0: REFA pin enabled.

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