AD9524BCPZ datasheet(40/56 Pages) AD

Part #	AD9524BCPZ

Description	Jitter Cleaner and Clock Generator

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Manufacturer	AD [Analog Devices]

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40 / 56 page

AD9524

Data Sheet

Rev. F | Page 40 of 56

Addr

(Hex)

Register

Name

(MSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

Bit 0

Default

Value

(Hex)

0x01D

PLL1 loop

filter zero

resistor control

Reserved

PLL1 loop filter, RZERO

0x00

Output PLL (PLL2)

0x0F0

PLL2 charge

pump control

PLL2 charge pump control

0x00

0x0F1

PLL2

feedback

N divider

control

A counter

B counter

0x04

0x0F2

PLL2 control

PLL2 lock

detector

power-

down

Reserved

Enable

frequency

doubler

Enable SPI

control of

antibacklash

pulse width

Antibacklash pulse

width control

PLL2 charge pump mode

0x03

0x0F3

VCO control

Reserved

Force release

of distribution

sync when

PLL2 is

unlocked

Reserved

Force

VCO to

midpoint

frequency

Calibrate VCO

(not auto-

clearing)

Reserved

0x00

0x0F4

VCO divider

control

Reserved

VCO

divider

power-

down

VCO divider

0x00

0x0F5

PLL2 loop

filter control

(9 bits)

Pole 2 resistor (RPOLE2)

Zero resistor (RZERO)

Pole 1 capacitor (CPOLE1)

0x00

0x0F6

Reserved

Bypass internal

RZERO resistor

0x00

0x0F9

Reserved

0x00

Clock Distribution

0x190

Reserved

0x00

0x196

Channel 0

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x00

0x197

10-bit channel divider[7:0] (LSB)

0x1F

0x198

Divider phase[5:0]

10-bit channel divider[9:8] (MSB)

0x04

0x199

Channel 1

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x20

0x19A

10-bit channel divider[7:0] (LSB)

0x1F

0x19B

Divider phase[5:0]

10-bit channel divider[9:8] (MSB)

0x04

0x19C

Channel 2

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x00

0x19D

10-bit channel divider[7:0] (LSB)

0x1F

0x19E

Divider phase[5:0]

10-bit channel divider[9:8] (MSB)

0x04

0x19F

Channel 3

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode[3:0]

0x20

0x1A0

10-bit channel divider[7:0] (LSB)

0x1F

0x1A1

Divider phase[5:0]

10-bit channel divider[9:8] (MSB)

0x04

0x1AE

Channel 4

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x00

0x1AF

10-bit channel divider[7:0] (LSB)

0x1F

0x1B0

Divider phase[5:0]

10-bit channel divider[9:8] (MSB)

0x04

0x1B1

Channel 5

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x20

0x1B2

10-bit channel divider[7:0] (LSB)

0x1F

0x1B3

Divider phase[5:0]

10-bit channel divider[9:8] (MSB)

0x04

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