AD9524BCPZ datasheet(33/56 Pages) AD

Part #	AD9524BCPZ

Description	Jitter Cleaner and Clock Generator

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Data Sheet

AD9524

Rev. F | Page 33 of 56

CS

SCLK

SDIO

tHIGH

tLOW

tCLK

tS

tDS

tDH

tC

BIT N

BIT N + 1

Figure 44. Serial Control Port Timing—Write

Table 28. Serial Control Port Timing

Parameter

Description

tDS

Setup time between data and rising edge of SCLK

tDH

Hold time between data and rising edge of SCLK

tCLK

Period of the clock

tS

Setup time between the CS falling edge and SCLK rising edge (start of communication cycle)

tC

Setup time between the SCLK rising edge and CS rising edge (end of communication cycle)

tHIGH

Minimum period that SCLK should be in a logic high state

tLOW

Minimum period that SCLK should be in a logic low state

tDV

SCLK to valid SDIO and SDO (see Figure 42)

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