AD9524BCPZ datasheet(31/56 Pages) AD

Part #	AD9524BCPZ

Description	Jitter Cleaner and Clock Generator

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Data Sheet

AD9524

Rev. F | Page 31 of 56

The default mode of the AD9524 serial control port is the

bidirectional mode. In bidirectional mode, both the sent data

and the readback data appear on the SDIO pin. It is also possible to

set the AD9524 to unidirectional mode. In unidirectional mode,

the readback data appears on the SDO pin.

A readback request reads the data that is in the serial control port

buffer area or the data that is in the active registers (see Figure 37).

SERIAL

CONTROL

PORT

BUFFER

REGISTERS

UPDATE

REGISTERS

ACTIVE

REGISTERS

SCLK/SCL

SDO

SDIO/SDA

CS

Figure 37. Relationship Between Serial Control Port Buffer Registers and

Active Registers

SPI INSTRUCTION WORD (16 BITS)

The MSB of the instruction word is R/W, which indicates

whether the instruction is a read or a write. The next two bits

([W1:W0]) indicate the length of the transfer in bytes. The final

13 bits are the address ([A12:A0]) at which to begin the read or

write operation.

For a write, the instruction word is followed by the number of

bytes of data indicated by Bits[W1:W0] (see Table 25).

Table 25. Byte Transfer Count

W1

W0

Bytes to Transfer

0

1

0

1

2

1

0

3

1

Streaming mode

Bits[A12:A0] select the address within the register map that is

written to or read from during the data transfer portion of the

communications cycle. Only Bits[A11:A0] are needed to cover

the range of the 0x234 registers used by the AD9524. Bit A12

must always be 0. For multibyte transfers, this address is the

starting byte address. In MSB first mode, subsequent bytes

decrement the address.

SPI MSB/LSB FIRST TRANSFERS

The AD9524 instruction word and byte data can be MSB first

or LSB first. Any data written to Register 0x000 must be mirrored:

Bit 7 is mirrored to Bit 0, Bit 6 to Bit 1, Bit 5 to Bit 2, and Bit 4 to

Bit 3. This makes it irrelevant whether LSB first or MSB first is

in effect. The default for the AD9524 is MSB first.

When LSB first is set by Register 0x000, Bit 1 and Register 0x000,

Bit 6, it takes effect immediately because it affects only the

operation of the serial control port and does not require that

an update be executed.

When MSB first mode is active, the instruction and data bytes

must be written from MSB to LSB. Multibyte data transfers in

MSB first format start with an instruction byte that includes the

register address of the most significant data byte. Subsequent

data bytes must follow in order from the high address to the

low address. In MSB first mode, the serial control port internal

address generator decrements for each data byte of the multibyte

transfer cycle.

When LSB first mode is active, the instruction and data bytes

must be written from LSB to MSB. Multibyte data transfers in

LSB first format start with an instruction byte that includes the

register address of the least significant data byte, followed by

multiple data bytes. In a multibyte transfer cycle, the internal

byte address generator of the serial port increments for each byte.

The AD9524 serial control port register address decrements

from the register address just written toward 0x000 for multibyte

I/O operations if the MSB first mode is active (default). If the

LSB first mode is active, the register address of the serial control

port increments from the address just written toward 0x234 for

multibyte I/O operations. Unused addresses are not skipped for

these operations.

For multibyte accesses that cross Address 0x234 or Address 0x000

in MSB first mode, the SPI internally disables writes to subsequent

registers and returns zeros for reads to subsequent registers.

Streaming mode always terminates when crossing address

boundaries (as shown in Table 26).

Table 26. Streaming Mode (No Addresses Are Skipped)

Write Mode

Address Direction

Stop Sequence

MSB First

Decrement

…, 0x001, 0x000, stop

Table 27. Serial Control Port, 16-Bit Instruction Word, MSB First

MSB

LSB

I15

I14

I13

I12

I11

I10

I9

I8

I7

I6

I5

I4

I3

I2

I1

I0

R/W

W1

W0

A12 = 0

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

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