AD9524BCPZ datasheet(28/56 Pages) AD

Part #	AD9524BCPZ

Description	Jitter Cleaner and Clock Generator

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AD9524

Data Sheet

Rev. F | Page 28 of 56

SDA

MSB

ACKNOWLEDGE FROM

SLAVE-RECEIVER

ACKNOWLEDGE FROM

SLAVE-RECEIVER

SCL

S

P

1

2

8

9

1

2

8

3 TO 7

9

10

Figure 32. Acknowledge Bit

SDA

MSB = 0

ACKNOWLEDGE FROM

SLAVE-RECEIVER

ACKNOWLEDGE FROM

SLAVE-RECEIVER

SCL

S

P

1

2

8

9

1

2

8

3 TO 7

9

10

Figure 33. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration)

SDA

ACKNOWLEDGE FROM

MASTER-RECEIVER

NO ACKNOWLEDGE

FROM

SLAVE-RECEIVER

SCL

S

P

1

2

8

9

1

2

8

3 TO 7

9

10

MSB = 1

Figure 34. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration)

The acknowledge bit is the ninth bit attached to any 8-bit data byte.

An acknowledge bit is always generated by the receiving device

(receiver) to inform the transmitter that the byte has been received.

It is accomplished by pulling the SDA line low during the ninth

clock pulse after each 8-bit data byte.

The no acknowledge bit is the ninth bit attached to any 8-bit data

byte. A no acknowledge bit is always generated by the receiving

device (receiver) to inform the transmitter that the byte has not

been received. It is accomplished by leaving the SDA line high

during the ninth clock pulse after each 8-bit data byte.

Data Transfer Process

The master initiates data transfer by asserting a start condition.

This indicates that a data stream follows. All I2C slave devices

connected to the serial bus respond to the start condition.

The master then sends an 8-bit address byte over the SDA line,

consisting of a 7-bit slave address (MSB first), plus an R/W bit.

This bit determines the direction of the data transfer, that is,

whether data is written to or read from the slave device

(0 = write, 1 = read).

The peripheral whose address corresponds to the transmitted

address responds by sending an acknowledge bit. All other

devices on the bus remain idle while the selected device waits

for data to be read from or written to it. If the R/W bit is 0, the

master (transmitter) writes to the slave device (receiver). If the R/W

bit is 1, the master (receiver) reads from the slave device (trans-

mitter). The format for these commands is described in the

Data Transfer Format section.

Data is then sent over the serial bus in the format of nine clock

pulses: one data byte (eight bits) from either master (write mode)

or slave (read mode), followed by an acknowledge bit from the

receiving device. The number of bytes that can be transmitted per

transfer is unrestricted. In write mode, the first two data bytes

immediately after the slave address byte are the internal memory

(control registers) address bytes with the high address byte first.

This addressing scheme gives a memory address of up to 216 − 1 =

65,535. The data bytes after these two memory address bytes are

register data written into the control registers. In read mode, the

data bytes after the slave address byte are register data read from

the control registers. A single I2C transfer can contain multiple data

bytes that can be read from or written to control registers whose

address is automatically incremented starting from the base

memory address.

When all data bytes are read or written, stop conditions are

established. In write mode, the master (transmitter) asserts a stop

condition to end data transfer during the 10th clock pulse following

the acknowledge bit for the last data byte from the slave device

(receiver). In read mode, the master device (receiver) receives the

last data byte from the slave device (transmitter) but does not pull

it low during the ninth clock pulse. This is known as a no acknowl-

edge bit. Upon receiving the no acknowledge bit, the slave device

knows that the data transfer is finished and releases the SDA line.

The master then takes the data line low during the low period

before the 10th clock pulse and high during the 10th clock pulse

to assert a stop condition.

A repeated start (Sr) condition can be used in place of a stop

condition. Furthermore, a start or stop condition can occur at

any time, and partially transferred bytes are discarded.

For an I2C data write transfer containing multiple data bytes,

the peripheral drives a no acknowledge for the data byte that

follows a write to Register 0x234, thereby ending the I2C transfer.

For an I2C data read transfer containing multiple data bytes,

the peripheral drives data bytes of 0x00 for subsequent reads that

follow a read from Register 0x234.

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