AD9523-1BCPZ datasheet(10/63 Pages) AD

Part #	AD9523-1BCPZ

Description	Low Jitter Clock Generator

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AD9523-1

Data Sheet

Rev. C | Page 10 of 63

JITTER AND NOISE CHARACTERISTICS

Table 10.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT ABSOLUTE RMS TIME JITTER

Application example based on a typical setup (see Table 3);

f = 122.88 MHz

LVPECL Mode, HSTL Mode, LVDS Mode

109

fs

Integrated BW = 200 kHz to 5 MHz

115

fs

Integrated BW = 200 kHz to 10 MHz

150

fs

Integrated BW = 12 kHz to 20 MHz

177

fs

Integrated BW = 10 kHz to 61 MHz

187

fs

Integrated BW = 1 kHz to 61 MHz

124

fs

Integrated BW = 1 MHz to 61 MHz

PLL2 CHARACTERISTICS

Table 11.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VCO (ON CHIP)

Frequency Range

2940

3100

MHz

Gain

45

MHz/V

PLL2 FIGURE OF MERIT (FOM)

−226

dBc/Hz

MAXIMUM PFD FREQUENCY

Antibacklash Pulse Width

High is the initial PLL2 antibacklash pulse width setting.

The user must program Register 0x019[4] = 1b to enable SPI

control of the antibacklash pulse width to the setting defined

in Register 0x00F2[3:2] and Table 46.

Minimum

259

MHz

Low

200

MHz

High

135

MHz

Maximum

80

MHz

LOGIC INPUT PINS—PD, SYNC, RESET, EEPROM_SEL, REF_SEL

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VOLTAGE

Input High

2.0

V

Input Low

0.8

V

INPUT LOW CURRENT

±80

±250

µA

The minus sign indicates that, due to the internal pull-up

resistor, current is flowing out of the AD9523-1

CAPACITANCE

3

pF

RESET TIMING

Pulse Width Low

50

ns

Inactive to Start of Register

Programming

100

ns

SYNC TIMING

Pulse Width Low

1.5

ns

High speed clock is the CLK input signal

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AD9523-1BCPZ Datasheet(PDF) 10 Page - Analog Devices

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