AD9523-1BCPZ datasheet(1/63 Pages) AD

Part #	AD9523-1BCPZ

Description	Low Jitter Clock Generator

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Low Jitter Clock Generator with

14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs

Data Sheet

AD9523-1

Rev. C

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Technical Support

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FEATURES

Output frequency: <1 MHz to 1 GHz

Start-up frequency accuracy: <±100 ppm (determined by

VCXO reference accuracy)

Zero delay operation

Input-to-output edge timing: <150 ps

Dual VCO dividers

14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS

14 dedicated output dividers with jitter-free adjustable delay

Adjustable delay: 63 resolution steps of ½ period of VCO

output divider

Output-to-output skew: <50 ps

Duty cycle correction for odd divider settings

Automatic synchronization of all outputs on power-up

Absolute output jitter: <150 fs at 122.88 MHz

Integration range: 12 kHz to 20 MHz

Broadband timing jitter: 124 fs

Digital lock detect

Nonvolatile EEPROM stores configuration settings

SPI- and I²C-compatible serial control port

Dual PLL architecture

PLL1

Low bandwidth for reference input clock cleanup with

external VCXO

Phase detector rate up to 130 MHz

Redundant reference inputs

Automatic and manual reference switchover modes

Revertive and nonrevertive switching

Loss of reference detection with holdover mode

Low noise LVCMOS output from VCXO used for RF/IF

synthesizers

PLL2

Phase detector rate up to 259 MHz

Integrated low noise VCO

APPLICATIONS

LTE and multicarrier GSM base stations

Wireless and broadband infrastructure

Medical instrumentation

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10G FC,

and other 10 Gbps protocols

Forward error correction (G.710)

High performance wireless transceivers

ATE and high performance instrumentation

FUNCTIONAL BLOCK DIAGRAM

PLL1

REFA,

REFA

REFB,

REFB

REF_TEST

SDIO/SDA

ZD_IN, ZD_IN

CONTROL

INTERFACE

(SPI AND I2C)

EEPROM

PLL2

ZERO

DELAY

AD9523-1

14-CLOCK

DISTRIBUTION

SCLK/SCL

SDO

OSC_IN, OSC_IN

DIVIDE-BY-

3, 4, 5

DIVIDE-BY-

3, 4, 5

8 OUTPUTS

OUT0,

OUT0

6 OUTPUTS

OUT3,

OUT3

OUT10,

OUT10

OUT13,

OUT13

OUT4,

OUT4

OUT9,

OUT9

Figure 1.

GENERAL DESCRIPTION

The AD9523-1 provides a low power, multi-output, clock

distribution function with low jitter performance, along with an

on-chip PLL and VCO with two VCO dividers. The on-chip VCO

tunes from 2.94 GHz to 3.1 GHz.

The AD9523-1 is designed to support the clock requirements

for long term evolution (LTE) and multicarrier GSM base

station designs. It relies on an external VCXO to provide the

reference jitter cleanup to achieve the restrictive low phase noise

requirements necessary for acceptable data converter SNR

performance.

The input receivers, oscillator, and zero delay receiver provide

both single-ended and differential operation. When connected

to a recovered system reference clock and a VCXO, the device

generates 14 low noise outputs with a range of 1 MHz to 1 GHz,

and one dedicated buffered output from the input PLL (PLL1).

The frequency and phase of one clock output relative to another

clock output can be varied by means of a divider phase select

function that serves as a jitter-free, coarse timing adjustment

in increments that are equal to half the period of the signal

coming out of the VCO.

An in-package EEPROM can be programmed through the serial

interface to store user-defined register settings for power-up

and chip reset.

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