AD9523-1BCPZ datasheet(8/63 Pages) AD

Part #	AD9523-1BCPZ

Description	Low Jitter Clock Generator

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AD9523-1

Data Sheet

Rev. C | Page 8 of 63

PLL1 OUTPUT CHARACTERISTICS

Table 7.

Parameter1

Min

Typ

Max

Unit

Test Conditions/Comments

MAXIMUM OUTPUT FREQUENCY

250

MHz

Rise Time/Fall Time (20% to 80%)

387

665

ps

15 pF load

Duty Cycle

45

50

55

%

f = 250 MHz

OUTPUT VOLTAGE HIGH

Output driver static

VDD3_PLL − 0.25

V

Load current = 10 mA

VDD3_PLL − 0.1

V

Load current = 1 mA

OUTPUT VOLTAGE LOW

Output driver static

0.2

V

Load current = 10 mA

0.1

V

Load current = 1 mA

MAXIMUM PFD FREQUENCY

Antibacklash Pulse Width

High is the initial PLL1 antibacklash pulse

width setting. The user must program

Register 0x019[4] = 1b to enable SPI

control of the antibacklash pulse width to

the setting defined in Register 0x019[3:2]

and Table 39.

Minimum

130

MHz

Low

90

MHz

High

65

MHz

Maximum

45

MHz

1 CMOS driver strength: strong (see Table 52).

OUT0, OUT0 TO OUT13, OUT13 DISTRIBUTION OUTPUT CHARACTERISTICS

Duty cycle performance is specified with the invert divider bit set to 1, and the divider phase bits set to 0.5. (For example, for Channel 0,

0x190[7] = 1 and 0x192[7:2] = 1.)

Table 8.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL MODE

Maximum Output Frequency

1

GHz

Minimum VCO/maximum dividers

Rise Time/Fall Time (20% to 80%)

117

147

ps

100 Ω termination across output pair

Duty Cycle

47

50

52

%

f < 500 MHz

43

48

52

%

f = 500 MHz to 800 MHz

40

49

54

%

f = 800 MHz to 1 GHz

Differential Output Voltage Swing

643

775

924

mV

Magnitude of voltage across pins; output

driver static

Common-Mode Output Voltage

VDD – 1.5

VDD − 1.4

VDD − 1.25

V

Output driver static

SCALED HSTL MODE, 16 mA

Maximum Output Frequency

1

GHz

Minimum VCO/maximum dividers

Rise Time/Fall Time (20% to 80%)

112

141

ps

100 Ω termination across output pair

Duty Cycle

47

50

52

%

f < 500 MHz

44

48

51

%

f = 500 MHz to 800 MHz

40

49

54

%

f = 800 MHz to 1 GHz

Differential Output Voltage Swing

1.3

1.6

1.7

mV

Nominal supply

Supply Sensitivity

0.6

mV/

mV

Change in output swing vs.

VDD3_OUT[x:y] (ΔVOD/ΔVDD3)

Common-Mode Output Voltage

VDD − 1.76

VDD − 1.6

VDD − 1.42

V

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