ad9523 datasheet(1/60 Pages) AD

Part #	AD9523

Description	Jitter Cleaner and Clock Generator

Download	60 Pages

Scroll/Zoom	100%

Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

Logo

1 / 60 page

Jitter Cleaner and Clock Generator with

14 Differential or 29 LVCMOS Outputs

Data Sheet

AD9523

Rev. D

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

FEATURES

Output frequency: <1 MHz to 1 GHz

Start-up frequency accuracy: <±100 ppm (determined by

VCXO reference accuracy)

Zero delay operation

Input-to-output edge timing: <150 ps

14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS

14 dedicated output dividers with jitter-free adjustable delay

Adjustable delay: 63 resolution steps of ½ period of VCO

output divider

Output-to-output skew: <50 ps

Duty cycle correction for odd divider settings

Automatic synchronization of all outputs on power-up

Absolute output jitter: <200 fs at 122.88 MHz

Integration range: 12 kHz to 20 MHz

Distribution phase noise floor: −160 dBc/Hz

Digital lock detect

Nonvolatile EEPROM stores configuration settings

SPI- and I²C-compatible serial control port

Dual PLL architecture

PLL1

Low bandwidth for reference input clock cleanup with

external VCXO

Phase detector rate up to130 MHz

Redundant reference inputs

Automatic and manual reference switchover modes

Revertive and nonrevertive switching

Loss of reference detection with holdover mode

Low noise LVCMOS output from VCXO used for RF/IF

synthesizers

PLL2

Phase detector rate up to 259 MHz

Integrated low noise VCO

APPLICATIONS

LTE and multicarrier GSM base stations

Wireless and broadband infrastructure

Medical instrumentation

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10G FC,

and other 10 Gbps protocols

Forward error correction (G.710)

High performance wireless transceivers

ATE and high performance instrumentation

FUNCTIONAL BLOCK DIAGRAM

PLL1

REFA,

REFA

OUT0,

OUT0

OUT1,

OUT1

OUT12,

OUT12

OUT13,

OUT13

REFB,

REFB

REF_TEST

SCLK/SCL

SDIO/SDA

SDO

ZD_IN, ZD_IN

CONTROL

INTERFACE

(SPI AND I2C)

EEPROM

PLL2

ZERO

DELAY

AD9523

14-CLOCK

DISTRIBUTION

OSC_IN, OSC_IN

Figure 1.

GENERAL DESCRIPTION

The AD9523 provides a low power, multi-output, clock distribution

function with low jitter performance, along with an on-chip PLL

and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz.

The AD9523 is designed to support the clock requirements for long

term evolution (LTE) and multicarrier GSM base station designs.

It relies on an external VCXO to provide the reference jitter cleanup

to achieve the restrictive low phase noise requirements necessary

for acceptable data converter SNR performance.

The input receivers, oscillator, and zero delay receiver provide

both single-ended and differential operation. When connected

to a recovered system reference clock and a VCXO, the device

generates 14 low noise outputs with a range of 1 MHz to 1 GHz,

and one dedicated buffered output from the input PLL (PLL1).

The frequency and phase of one clock output relative to another

clock output can be varied by means of a divider phase select

function that serves as a jitter-free coarse timing adjustment in

increments that are equal to half the period of the signal coming

out of the VCO.

An in-package EEPROM can be programmed through the serial

interface to store user-defined register settings for power-up and

chip reset.

Similar Part No. - AD9523

Manufacturer	Part #	Datasheet	Description
Analog Devices	AD9523	879Kb / 60P	Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs REV. C
	AD9523-1	1Mb / 63P	Low Jitter Clock Generator
	AD9523-1/PCBZ	840Kb / 60P	Low Jitter Clock Generator REV. B
	AD9523-1BCPZ	840Kb / 60P	Low Jitter Clock Generator REV. B
	AD9523-1BCPZ	1Mb / 63P	Low Jitter Clock Generator

More results

Similar Description - AD9523

Manufacturer	Part #	Datasheet	Description
Analog Devices	AD9524	973Kb / 56P	Jitter Cleaner and Clock Generator
Texas Instruments	CDCM6208V1F	2Mb / 87P	[Old version datasheet] 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
	LMK04100	1Mb / 52P	[Old version datasheet] Family Clock Jitter Cleaner
	CDCM6208	2Mb / 89P	[Old version datasheet] 2:8 Clock Generator, Jitter Cleaner With Fractional Dividers
	CDCM6208	2Mb / 92P	[Old version datasheet] 2:8 Clock Generator, Jitter Cleaner With Fractional Dividers
Analog Devices	AD9524BCPZ	925Kb / 56P	Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs Rev. E
Analog Devices	AD9524	863Kb / 56P	Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs REV. D
Texas Instruments	CDCM6208	2Mb / 78P	[Old version datasheet] 2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS
	LMK04803	2Mb / 139P	[Old version datasheet] Low-Noise Clock Jitter Cleaner
	CDCM6208V2G	2Mb / 88P	[Old version datasheet] CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

More results

AD9523 Datasheet(PDF) 1 Page - Analog Devices

AD9523 Datasheet(HTML) 1 Page - Analog Devices

Similar Part No. - AD9523

Similar Description - AD9523

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL