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AD9523 Datasheet(PDF) 53 Page - Analog Devices

Part # AD9523
Description  Jitter Cleaner and Clock Generator
Download  60 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9523 Datasheet(HTML) 53 Page - Analog Devices

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Data Sheet
AD9523
Rev. D | Page 53 of 60
Table 48. VCO Control
Address
Bits
Bit Name
Description
0x0F3
[7:5]
Reserved
Reserved.
4
Force release of distribution
sync when PLL2 is unlocked
0 (default): distribution is held in sync (static) until the output PLL locks for the first
time. Then it is automatically released from sync with all dividers synchronized.
1: overrides the PLL2 lock detector state; forces release of the distribution from sync.
3
Treat reference as valid
0 (default): uses the PLL1 VCXO indicator to determine when the reference clock to
the PLL2 is valid.
1: treats the reference clock as valid even if PLL1 does not consider it to be valid.
2
Force VCO to midpoint frequency
Selects VCO control voltage functionality.
0 (default): normal VCO operation.
1: forces VCO control voltage to midscale.
1
Calibrate VCO (not autoclearing)
1: initiates VCO calibration (this is not an autoclearing bit).
0: resets the VCO calibration.
0
Reserved
Reserved.
Table 49. VCO Divider Control
Address
Bits
Bit Name
Description
0x0F4
[7:4]
Reserved
Reserved.
3
VCO divider power-down
1: powers down the divider.
0: normal operation.
[2:0]
VCO divider
Note that the VCO divider connects to all output channels.
Bit 2
Bit 1
Bit 0
Divider Value
0
0
0
Divide-by-4
0
0
1
Divide-by-5
0
1
0
Divide-by-6
0
1
1
Divide-by-7
1
0
0
Divide-by-8
1
0
1
Divide-by-9
1
1
0
Divide-by-10
1
1
1
Divide-by-11


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