AD9523 datasheet(28/60 Pages) AD

Part #	AD9523

Description	Jitter Cleaner and Clock Generator

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AD9523

Data Sheet

Rev. D | Page 28 of 60

SERIAL CONTROL PORT

The AD9523 serial control port is a flexible, synchronous serial

communications port that allows an easy interface with many

industry-standard microcontrollers and microprocessors.

The AD9523 serial control port is compatible with most

synchronous transfer formats, including I2C, Motorola® SPI,

and Intel® SSR protocols. The AD9523 I2C implementation

deviates from the classic I2C specification in two specifications,

and these deviations are documented in Table 16. The serial

control port allows read/write access to all registers that

configure the AD9523.

SPI/I²C PORT SELECTION

The AD9523 has two serial interfaces, SPI and I2C. Users can

select either the SPI or I2C depending on the states (logic high,

logic low) of the two logic level input pins, SP1 and SP0, when

power is applied or after a RESET (each pin has an internal

40 kΩ pull-down resistor). When both SP1 and SP0 are low, the

SPI interface is active. Otherwise, I2C is active with three

different I2C slave address settings (seven bits wide), as shown

in Table 22. The five MSBs of the slave address are hardware

coded as 11000, and the two LSBs are determined by the logic

levels of the SP1 and SP0 pins.

Table 22. Serial Port Mode Selection

SP1

SP0

Address

Low

SPI

Low

High

I2C: 1100000

High

Low

I2C: 1100001

High

I2C: 1100010

I²C SERIAL PORT OPERATION

The AD9523 I2C port is based on the I2C fast mode standard.

The AD9523 supports both I2C protocols: standard mode

(100 kHz) and fast mode (400 kHz).

The AD9523 I2C port has a 2-wire interface consisting of a

serial data line (SDA) and a serial clock line (SCL). In an I2C

bus system, the AD9523 is connected to the serial bus (data bus

SDA and clock bus SCL) as a slave device, meaning that no clock

is generated by the AD9523. The AD9523 uses direct 16-bit

(two bytes) memory addressing instead of traditional 8-bit

(one byte) memory addressing.

I²C Bus Characteristics

Table 23. I2C Bus Definitions

Abbreviation

Definition

S

Start

Sr

Repeated start

P

Stop

A

Acknowledge

A

No acknowledge

W

Write

R

Read

One pulse on the SCL clock line is generated for each data bit

that is transferred.

The data on the SDA line must not change during the high period

of the clock. The state of the data line can change only when the

clock on the SCL line is low.

SDA

SCL

DATA LINE

STABLE;

DATA VALID

CHANGE

OF DATA

ALLOWED

Figure 30. Valid Bit Transfer

A start condition is a transition from high to low on the SDA

line while SCL is high. The start condition is always generated

by the master to initialize the data transfer.

A stop condition is a transition from low to high on the SDA

line while SCL is high. The stop condition is always generated

by the master to end the data transfer.

START

CONDITION

S

STOP

CONDITION

P

SDA

SCL

Figure 31. Start and Stop Conditions

A byte on the SDA line is always eight bits long. An acknowledge

bit must follow every byte. Bytes are sent MSB first.

The acknowledge bit is the ninth bit attached to any 8-bit data byte.

An acknowledge bit is always generated by the receiving device

(receiver) to inform the transmitter that the byte has been received.

The acknowledge bit is accomplished by pulling the SDA line low

during the ninth clock pulse after each 8-bit data byte.

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