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AD9523 Datasheet(PDF) 26 Page - Analog Devices |
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AD9523 Datasheet(HTML) 26 Page - Analog Devices |
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26 / 60 page  AD9523 Data Sheet Rev. D | Page 26 of 60 ZERO DELAY OPERATION Zero delay operation aligns the phase of the output clocks with the phase of the external PLL reference input. The OUT0 output is designed to be used as the output for zero delay. There are two zero delay modes on the AD9523: internal and external (see Figure 29). Note that the external delay mode provides better matching than the internal delay mode because the output drivers are included in the zero delay path. INTERNAL FB ZD_IN REFA REFA AD9523 FEEDBACK DELAY REF DELAY ENB PFD OUT0 OUT0 ZD_IN Figure 29. Zero Delay Function Internal Zero Delay Mode The internal zero delay function of the AD9523 is achieved by feeding the output of Channel Divider 0 back to the PLL1 N divider. Register 0x01B[5] is used to select internal zero delay mode (see Table 42). In the internal zero delay mode, the output of Channel Divider 0 is routed back to the PLL1 (N divider) through a mux. PLL1 synchronizes the phase/edge of the output of Channel Divider 0 with the phase/edge of the reference input. Because the channel dividers are synchronized to each other, the outputs of the channel divider are synchronous with the reference input. External Zero Delay Mode The external zero delay function of the AD9523 is achieved by feeding OUT0 back to the ZD_IN input and, ultimately, back to the PLL1 N divider. In Figure 29, the change in signal routing for external zero delay is external to the AD9523. Register 0x01B[5] is used to select the external zero delay mode. In external zero delay mode, OUT0 must be routed back to PLL1 (the N divider) through the ZD_IN and ZD_IN pins. PLL1 synchronizes the phase/edge of the feedback output clock with the phase/edge of the reference input. Because the channel dividers are synchronized to each other, the clock outputs are synchronous with the reference input. Both the reference path delay and the feedback delay from ZD_IN are designed to have the same propagation delay from the output drivers and PLL components to minimize the phase offset between the clock output and the reference input to achieve zero delay. LOCK DETECT The PLL1 and PLL2 lock detectors issue an unlock condition when the frequency error is greater than the threshold of the lock detector. When the PLL is unlocked, there is a random phase between the reference clock and feedback clock. Due to the random phase relationship that exists, the unlock condition can take between 215 × TPFD cycles to 1 × TPFD cycles. A lock condition always takes 216 × TPFD to lock, but can potentially take 231 × TPFD cycles depending on how big the phase jump is and when it occurs in relation to the lock detect restart. RESET MODES The AD9523 has a power-on reset (POR) and several other ways to apply a reset condition to the chip. Power-On Reset During chip power-up, a power-on reset pulse is issued when the 3.3 V supply reaches ~2.6 V (<2.8 V) and restores the chip either to the setting stored in the EEPROM (EEPROM pin = 1) or to the on-chip setting (EEPROM pin = 0). At power-on, the AD9523 executes a sync operation, which brings the outputs into phase alignment according to the default settings. The output drivers are held in sync for the duration of the internally generated power-up sync timer (~70 ms). The outputs begin to toggle after this period. Reset via the RESET Pin RESET, a reset (an asynchronous hard reset is executed by briefly pulling RESET low), restores the chip either to the setting stored in the EEPROM (EEPROM pin = 1) or to the on-chip setting (EEPROM pin = 0). A reset also executes a sync operation, which brings the outputs into phase alignment according to the default settings. When the EEPROM is inactive (EEPROM pin = 0), it takes ~2 µs for the outputs to begin toggling after RESET is issued. When the EEPROM is active (EEPROM pin = 1), it takes ~40 ms for the outputs to toggle after RESET is brought high. Reset via the Serial Port The serial port control register allows for a reset by setting Bit 2 and Bit 5 in Register 0x000. When Bit 2 and Bit 5 are set, the chip enters a reset mode and restores the chip either to the setting stored in the EEPROM (EEPROM pin = 1) or to the on-chip setting (EEPROM pin = 0), except for Register 0x000. Except for the self-clearing bits, Bit 2 and Bit 5, Register 0x000 retains its previous value prior to reset. During the internal reset, the outputs hold static. Bit 2 and Bit 5 are self-clearing. However, the self-clearing operation does not complete until an additional serial port SCLK cycle completes, and the AD9523 is held in reset until Bit 2 and Bit 5 self-clear. Reset to Settings in EEPROM when EEPROM Pin = 0 via the Serial Port The serial port control register allows the chip to be reset to settings in the EEPROM when the EEPROM pin = 0 via Register 0xB02[1]. This bit is self-clearing. This bit does not have any effect when the EEPROM pin = 1. It takes ~40 ms for the outputs to begin toggling after the SOFT_EEPROM register is cleared. |
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