Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

AD9523 Datasheet(PDF) 24 Page - Analog Devices

Part # AD9523
Description  Jitter Cleaner and Clock Generator
Download  60 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9523 Datasheet(HTML) 24 Page - Analog Devices

Back Button AD9523 Datasheet HTML 20Page - Analog Devices AD9523 Datasheet HTML 21Page - Analog Devices AD9523 Datasheet HTML 22Page - Analog Devices AD9523 Datasheet HTML 23Page - Analog Devices AD9523 Datasheet HTML 24Page - Analog Devices AD9523 Datasheet HTML 25Page - Analog Devices AD9523 Datasheet HTML 26Page - Analog Devices AD9523 Datasheet HTML 27Page - Analog Devices AD9523 Datasheet HTML 28Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 24 / 60 page
background image
AD9523
Data Sheet
Rev. D | Page 24 of 60
CLOCK DISTRIBUTION
The clock distribution block provides an integrated solution for
generating multiple clock outputs based on frequency dividing
the PLL2 VCO divider output. The distribution output consists
of 14 channels (OUT0 to OUT13). Each of the output channels
has a dedicated divider and output driver, as shown in Figure 27.
The AD9523 also has the capability to route the VCXO output
to four of the outputs (OUT0 to OUT3).
Clock Dividers
The output clock distribution dividers are referred to as D0 to
D13, corresponding to output channels OUT0 through OUT13,
respectively. Each divider is programmable with 10 bits of division
depth that is equal to 1 to 1024. Dividers have duty cycle correction
to always give a 50% duty cycle, even for odd divides.
Output Power-Down
Each of the output channels offers independent control of the
power-down functionality via the Channel 0 to Channel 13
control registers (see Table 51). Each output channel has a
dedicated power-down bit for powering down the output driver.
However, if all 14 outputs are powered down, the entire
distribution output enters a deep sleep mode. Although each
channel has a channel power-down control signal, it may
sometimes be desirable to power down an output driver while
maintaining the divider’s synchronization with the other
channel dividers. This is accomplished by placing the output
in tristate mode (this works in CMOS mode, as well).
Multimode Output Drivers
The user has independent control of the operating mode of each of
the fourteen output channels via the Channel 0 to Channel 13
control registers (see Table 51). The operating mode control
includes the following:
Logic family and pin functionality
Output drive strength
Output polarity
The four least significant bits (LSBs) of each of the 14 Channel 0
to Channel 13 control registers comprise the driver mode bits. The
mode value selects the desired logic family and pin functionality
of an output channel, as listed in Table 51. This driver design
allows a common 100 Ω external resistor for all the different
driver modes of operation that are illustrated in Figure 26.
If the output channel is ac-coupled to the circuit to be clocked,
changing the mode varies the voltage swing to determine sensitivity
to the drive level. For example, in LVDS mode, a current of 3.5 mA
causes a 350 mV peak voltage. Likewise, in LVPECL mode, a
current of 8 mA causes an 800 mV peak voltage at the 100 Ω
load resistor. Using any termination other than those specified
in the Input/Output Termination Recommendations section
may results in damage or decrease end of life performance.
In addition to the four mode bits, each of the 14 Channel 0 to
Channel 13 control registers includes the following control bits:
Invert divider output. Enables the user to choose between
normal polarity and inverted polarity. Normal polarity is
the default state. Inverted polarity reverses the representation
of Logic 0 and Logic 1, regardless of the logic family.
Ignore sync. Makes the divider ignore the SYNC signal
from any source.
Power down channel. Powers down the entire channel.
Lower power mode.
Driver mode.
Channel divider.
Divider phase.
3.5mA/8mA
LVDS/LVPECL
ENABLED
HSTL
ENABLED
HSTL
ENABLED
50Ω
50Ω
P
N
N
P
100Ω LOAD
CM
VDD3_OUT[x:y]
1.25V LVDS
VDD – 1.3V LVPECL
CM
COMMON-MODE
CIRCUIT
+
Figure 26. Multimode Driver
Clock Distribution Synchronization
A block diagram of the clock distribution synchronization
functionality is shown in Figure 27. The synchronization
sequence begins with the primary synchronization signal,
which ultimately results in delivery of a synchronization strobe
to the clock distribution logic.
As indicated, the primary synchronization signal originates
from one of the following sources:
Direct synchronization source via the sync dividers bit (see
Register 0x232[0] in Table 55)
Device pin, SYNC (Pin 17)
An automatic synchronization of the divider is initiated the first
time that PLL2 locks after a power-up or reset event. Subsequent
lock/unlock events do not initiate a resynchronization of the
distribution dividers unless they are preceded by a power-down
or reset of the part. Both sources of the primary synchronization
signal are logic OR’d; therefore, any one of them can synchronize
the clock distribution output at any time.


Similar Part No. - AD9523

ManufacturerPart #DatasheetDescription
logo
Analog Devices
AD9523 AD-AD9523 Datasheet
879Kb / 60P
   Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs
REV. C
AD9523-1 AD-AD9523-1 Datasheet
1Mb / 63P
   Low Jitter Clock Generator
AD9523-1/PCBZ AD-AD9523-1/PCBZ Datasheet
840Kb / 60P
   Low Jitter Clock Generator
REV. B
AD9523-1BCPZ AD-AD9523-1BCPZ Datasheet
840Kb / 60P
   Low Jitter Clock Generator
REV. B
AD9523-1BCPZ AD-AD9523-1BCPZ Datasheet
1Mb / 63P
   Low Jitter Clock Generator
More results

Similar Description - AD9523

ManufacturerPart #DatasheetDescription
logo
Analog Devices
AD9524 AD-AD9524_15 Datasheet
973Kb / 56P
   Jitter Cleaner and Clock Generator
logo
Texas Instruments
CDCM6208V1F TI1-CDCM6208V1F Datasheet
2Mb / 87P
[Old version datasheet]   2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
LMK04100 TI1-LMK04100_14 Datasheet
1Mb / 52P
[Old version datasheet]   Family Clock Jitter Cleaner
CDCM6208 TI1-CDCM6208_14 Datasheet
2Mb / 89P
[Old version datasheet]   2:8 Clock Generator, Jitter Cleaner With Fractional Dividers
CDCM6208 TI1-CDCM6208_18 Datasheet
2Mb / 92P
[Old version datasheet]   2:8 Clock Generator, Jitter Cleaner With Fractional Dividers
logo
Analog Devices
AD9524BCPZ AD-AD9524BCPZ Datasheet
925Kb / 56P
   Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs
Rev. E
AD9524 AD-AD9524 Datasheet
863Kb / 56P
   Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs
REV. D
logo
Texas Instruments
CDCM6208 TI-CDCM6208 Datasheet
2Mb / 78P
[Old version datasheet]   2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS
LMK04803 TI1-LMK04803_14 Datasheet
2Mb / 139P
[Old version datasheet]   Low-Noise Clock Jitter Cleaner
CDCM6208V2G TI1-CDCM6208V2G Datasheet
2Mb / 88P
[Old version datasheet]   CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com