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AD9523 Datasheet(PDF) 23 Page - Analog Devices |
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AD9523 Datasheet(HTML) 23 Page - Analog Devices |
23 / 60 page ![]() Data Sheet AD9523 Rev. D | Page 23 of 60 PLL2 Loop Filter The PLL2 loop filter requires the connection of an external capacitor from LF2_EXT_CAP (Pin 11) to LDO_VCO (Pin 14), as illustrated in Figure 25. The value of the external capacitor depends on the operating mode and the desired phase noise performance. For example, a loop bandwidth of approximately 500 kHz produces the lowest integrated jitter. A lower bandwidth produces lower phase noise at 1 MHz but increases the total integrated jitter. Table 21. PLL2 Loop Filter Programmable Values RZERO (Ω) CPOLE1 (pF) RPOLE2 (Ω) CPOLE2 (pF) LF2_EXT_CAP1 (pF) 3250 48 900 Fixed at 16 Typical at 1000 3000 40 450 2750 32 300 2500 24 225 2250 16 2100 8 2000 0 1850 1 External loop filter capacitor. VCO Divider The VCO divider provides frequency division between the internal VCO and the clock distribution. The VCO divider can be set to divide by 4, 5, 6, 7, 8, 9, 10, or 11. VCO and VCO Calibration The AD9523 on-chip VCO must be manually calibrated to ensure proper operation over process and temperature. A VCO calibration is accomplished by transitioning the calibrate VCO bit (Register 0x0F3[1]) from 0 to 1 (this bit is not self clearing). The setting can be performed as part of the initial setup before executing the IO_UPDATE bit (Register 0x234[1] = 1b). A readback bit, VCO calibration in progress (Register 0x22D[0]), indicates when a VCO calibration is in progress by returning a logic true (Register 0x22D[1] = 1b). If the EEPROM is in use, setting the calibrate VCO bit to 1 before saving the register settings to the EEPROM ensures that the VCO calibrates automatically after the EEPROM has loaded. After calibration, it is recommended to initiate a distribution sync (see the Clock Distribution Synchronization section). Note that the calibrate VCO bit defaults to 0. This bit must change from 0 to 1 to initiate a calibration sequence. Therefore, any subsequent calibrations require the following sequence: 1. Register 0x0F3[1] = 0b (calibrate VCO bit) 2. Register 0x234[0] = 1b (IO_UPDATE bit) 3. Register 0x0F3[1] = 1b (calibrate VCO bit) 4. Register 0x234[0] =1b (IO_UPDATE bit) VCO calibration is controlled by a calibration controller that runs off the OSC_IN input clock. The calibration requires that PLL2 be set up properly to lock the PLL2 loop and that the OSC_IN clock be present. During power-up or reset, the distribution section is automatically held in sync until the first VCO calibration is finished. Therefore, no outputs can occur until VCO calibration is complete and PLL2 is locked. This default functionality can be overwritten using Register 0x0F3[4]. Initiate a VCO calibration under the following conditions: • After changing any of the PLL2 B counter and A counter settings or after a change in the PLL2 reference clock frequency. This means that a VCO calibration should be initiated any time that a PLL2 register or reference clock changes such that a different VCO frequency is the result. • Whenever system calibration is desired. The VCO is designed to operate properly over extremes of temperature even when it is first calibrated at the opposite extreme. However, a VCO calibration can be initiated at any time, if desired. |
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