AD9523 datasheet(22/60 Pages) AD

Part #	AD9523

Description	Jitter Cleaner and Clock Generator

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AD9523

Data Sheet

Rev. D | Page 22 of 60

COMPONENT BLOCKS—OUTPUT PLL (PLL2)

PLL2 General Description

The output PLL (referred to as PLL2) consists of an optional

input reference doubler, phase/frequency detector (PFD),

a partially integrated analog loop filter (see Figure 25), an

integrated voltage controlled oscillator (VCO), and a feedback

divider. The VCO produces a nominal 3.8 GHz signal with an

output divider that is capable of division ratios of 4 to 11.

The PFD of the output PLL drives a charge pump that increases,

decreases, or holds constant the charge stored on the loop filter

capacitors (both internal and external). The stored charge results

in a voltage that sets the output frequency of the VCO. The

feedback loop of the PLL causes the VCO control voltage to

vary in a way that phase locks the PFD input signals. The gain

of PLL2 is proportional to the current delivered by the charge

pump. The loop filter bandwidth is chosen to reduce noise

contributions from PLL sources that could degrade phase noise

requirements.

The output PLL has a VCO with multiple bands spanning a

range of 3.6 GHz to 4.0 GHz. However, the actual operating

frequency within a particular band depends on the control

voltage that appears on the loop filter capacitor. The control

voltage causes the VCO output frequency to vary linearly within

the selected band. This frequency variability allows the control

loop of the output PLL to synchronize the VCO output signal

with the reference signal applied to the PFD. Typically, the

device automatically selects the appropriate band as part of

its calibration process (invoked via the VCO control register

at Address 0x0F3). The VCO is designed to operate over

temperature extremes including when the VCO is calibrated

at one temperature extreme and operated within another.

Input 2× Frequency Multiplier

The 2× frequency multiplier provides the option to double

the frequency at the PLL2 input. This allows the user to take

advantage of a higher frequency at the input to the PLL (PFD)

and, thus, allows for reduced in-band phase noise and greater

separation between the frequency generated by the PLL and the

modulation spur associated with PFD. However, increased

reference spur separation results in harmonic spurs introduced

by the frequency multiplier that increase as the duty cycle

deviates from 50% at the OSC_IN inputs. Therefore, beneficial

use of the frequency multiplier is application-specific. Typically,

a VCXO with proper interfacing has a duty cycle that is

approximately 50% at the OSC_IN inputs. Note that the

maximum output frequency of the 2× frequency multipliers

must not exceed the maximum PFD rate that is specified in

Table 12.

PLL2 Feedback Divider

PLL2 has a feedback divider (N divider) that enables it to provide

integer frequency up-conversion. The PLL2 N divider is a

combination of a prescaler (P) and two counters, A and B.

The total divider value is

N

= (P × B) + A

where P = 4.

The feedback divider is a dual modulus prescaler architecture,

with a nonprogrammable P that is equal to 4. The value of the

B counter can be from 4 to 63, and the value of the A counter can

be from 0 to 3. However, due to the architecture of the divider,

there are constraints, as listed in Table 46.

N DIVIDER

TO DIST/

RESYNC

×2

PLL1_OUT

LDO

PLL_1.8V

LDO_PLL2

VDD3_PLL2

LDO_VCO

DIVIDE BY

1, 2, 4, 8, 16

DIVIDE BY

4, 5, 6, ...11

DIVIDE-BY-4

PRESCALER

A/B

COUNTERS

CHARGE PUMP

8 BITS, 3.5µA LSB

PFD

RZERO

RPOLE2

CPOLE1

CPOLE2

LF2_EXT_CAP

AD9523

Figure 25. Output PLL (PLL2) Block Diagram

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