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AD9523 Datasheet(PDF) 21 Page - Analog Devices

Part # AD9523
Description  Jitter Cleaner and Clock Generator
Download  60 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9523 Datasheet(HTML) 21 Page - Analog Devices

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Data Sheet
AD9523
Rev. D | Page 21 of 60
PLL1 Input Dividers
Each reference input feeds a dedicated reference divider block.
The input dividers provide division of the reference frequency
in integer steps from 1 to 1023. They provide the bulk of the
frequency prescaling that is necessary to reduce the reference
frequency to accommodate the bandwidth that is typically
desired for PLL1.
PLL1 Reference Switchover
The reference monitor verifies the presence/absence of the
prescaled REFA and REFB signals (that is, after division by the
input dividers). The status of the reference monitor guides the
activity of the switchover control logic. The AD9523 supports
automatic and manual PLL reference clock switching between
REFA (the REFA and REFA pins) and REFB (the REFB and
REFB pins). This feature supports networking and infrastructure
applications that require redundant references.
There are several configurable modes of reference switchover.
Manual reference switchover is achieved either via a
programming register setting or by using the REF_SEL pin.
Automatic reference switchover occurs when REFA disappears
and there is a reference on REFB.
Automatic reference switchover can be set to work as follows:
Nonrevertive: stay on REFB. Switch from REFA to REFB
when REFA disappears, but do not switch back to REFA
if it reappears. If REFB disappears, then go back to REFA.
Revert to REFA: switch from REFA to REFB when REFA
disappears. Return to REFA from REFB when REFA returns.
See Table 43 for the PLL1 miscellaneous control register bit settings.
PLL1 Holdover
In the absence of both input references, the device enters
holdover mode. Holdover is a secondary function that is
provided by PLL1. Because PLL1 has an external VCXO
available as a frequency source, it continues to operate in the
absence of the input reference signals. When the device
switches to holdover, the charge pump tristates. The device
continues operating in this mode until a reference signal
becomes available. Then the device exits holdover mode,
and PLL1 resynchronizes with the active reference. In addition
to tristate, the charge pump can be forced to VCC/2 during
holdover (see Table 43, Register 0x01C[6]).


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