AD9523 datasheet(12/60 Pages) AD

Part #	AD9523

Description	Jitter Cleaner and Clock Generator

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AD9523

Data Sheet

Rev. D | Page 12 of 60

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

LDO_PLL1

VDD3_PLL1

REFA

REFB

LF1_EXT_CAP

OSC_CTRL

OSC_IN

LF2_EXT_CAP

LDO_PLL2

VDD3_PLL2

LDO_VCO

PD

REF_SEL

17

SYNC

18

VDD3_REF

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

VDD1.8_OUT[4:5]

OUT4

VDD3_OUT[4:5]

OUT5

VDD1.8_OUT[6:7]

OUT6

VDD3_OUT[6:7]

OUT7

VDD1.8_OUT[8:9]

OUT8

VDD3_OUT[8:9]

OUT9

PIN 1

INDICATOR

AD9523

(TOP VIEW)

NOTES

1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND.

AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT.

ON EXISTING PCB DESIGNS, IT ISACCEPTABLE TO LEAVE PIN 69 CONNECTED TO 1.8V SUPPLY.

2. THE EXPOSED PADDLE IS THE GROUND CONNECTION ON THE CHIP. IT MUST BE SOLDERED TO THE

ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND

MECHANICAL STRENGTH BENEFITS.

Figure 2. Pin Configuration

Table 19. Pin Function Descriptions

No.

Mnemonic

Type1

Description

1

LDO_PLL1

P/O

1.8 V Internal LDO Regulator Decoupling Pin for PLL1. Connect a 0.47 µF decoupling capacitor from

this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in

close proximity to the device.

2

VDD3_PLL1

P

3.3 V Supply PLL1. Use the same supply as VCXO.

3

REFA

I

Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

4

REFA

I

Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for the

PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3V CMOS input.

5

REFB

I

Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

6

REFB

I

Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL

reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

7

LF1_EXT_CAP

O

PLL1 External Loop Filter Capacitor. Connect a loop filter capacitor to this pin and to ground.

8

OSC_CTRL

O

Oscillator Control Voltage. Connect this pin to the voltage control pin of the external oscillator.

9

OSC_IN

I

PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

10

OSC_IN

I

Complementary PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL

reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

11

LF2_EXT_CAP

O

PLL2 External Loop Filter Capacitor Connection. Connect a capacitor to this pin and LDO_VCO.

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