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AD9523 Datasheet(PDF) 52 Page - Analog Devices |
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AD9523 Datasheet(HTML) 52 Page - Analog Devices |
52 / 60 page ![]() AD9523 Data Sheet Rev. D | Page 52 of 60 Output PLL (PLL2) (Address 0x0F0 to Address 0x0F6) Table 45. PLL2 Charge Pump Control Table 46. PLL2 Feedback N Divider Control Table 47. PLL2 Control Address Bits Bit Name Description 0x0F2 7 PLL2 lock detector power-down Controls power-down of the PLL2 lock detector. 1: lock detector powered down. 0: lock detector active. 6 Reserved Default = 0; value must remain 0. 5 Enable frequency doubler Enables doubling of the PLL2 reference input frequency. 1: enabled. 0: disabled. 4 Enable SPI control of antibacklash pulse width Setting this bit allows user control of the antibacklash pulse width setting in Register 0x0F2[3:2]. 0 (default): antibacklash period is forced to high. 1: antibacklash period defined by Register 0x0F[3:2] (recommended setting). [3:2] Antibacklash pulse width control Controls the PFD antibacklash period. These bits default to the high setting unless reprogrammed using Register 0x0F2[4] = 1b. The high setting decreases the maximum allowable PLL2 PFD rate. See Table 12 for ranges. 00 minimum. 01: low. 10: high (initial state unless changed via Register 0x0F2[4] = 1b). 11: maximum. [1:0] PLL2 charge pump mode Controls the mode of the PLL2 charge pump. 00: tristate. 01: pump up. 10: pump down. 11 (default): normal. Address Bits Bit Name Description 0x0F0 [7:0] PLL2 charge pump control These bits set the magnitude of the PLL2 charge pump current. Granularity is ~3.5 µA with a full-scale magnitude of ~900 µA. Address Bits Bit Name Description 0x0F1 [7:6] A counter A counter word. [5:0] B counter B counter word. Feedback Divider Constraints A Counter (Bits[7:6]) B Counter (Bits[5:0]) Allowed N Division (4 × B + A) A = 0 or A = 1 B = 4 16, 17 A = 0 to A = 2 B = 5 20, 21, 22 A = 0 to A = 2 B = 6 24, 25, 26 A = 0 to A = 3 B ≥ 7 28, 29 … continuous to 255 |
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