AD9523 datasheet(49/60 Pages) AD

Part #	AD9523

Description	Jitter Cleaner and Clock Generator

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49 / 60 page

Data Sheet

AD9523

Rev. D | Page 49 of 60

Input PLL (PLL1) (Address 0x010 to Address 0x01D)

Table 35. PLL1 REFA R Divider Control

Address

Bits

Bit Name

Description

0x010

[7:0]

REFA R divider

10-bit REFA R divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.

00000000, 00000001: divide-by-1.

0x011

[1:0]

REFA R divider

10-bit REFA R divider, Bits[9:8] (MSB).

Table 36. PLL1 REFB R Divider Control1

Address

Bits

Bit Name

Description

0x012

[7:0]

REFB R divider

10-bit REFB R divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.

00000000, 00000001: divide-by-1.

0x013

[1:0]

REFB R divider

10-bit REFB R divider, Bits[9:8] (MSB).

1 Requires Register 0x01C[7] = 1b for division that is independent of REFA division.

Table 37. PLL1 Reference Test Divider

Address

Bits

Bit Name

Description

0x014

[7:6]

Reserved

[5:0]

REF_TEST divider

6-bit reference test divider. Divide-by-1 to divide-by-63.

000000, 000001: divide-by-1.

Table 38. PLL1 Reserved

Address

Bits

Bit Name

Description

0x015

[7:0]

Reserved

Table 39. PLL1 Feedback N Divider Control

Address

Bits

Bit Name

Description

0x016

[7:0]

PLL1 feedback N divider control

(N_PLL1)

10-bit feedback divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.

00000000, 00000001: divide-by-1.

0x017

[1:0]

PLL1 feedback N divider control

(N_PLL1)

10-bit feedback divider, Bits[1:0] (MSB).

Table 40. PLL1 Charge Pump Control

Address

Bits

Bit Name

Description

0x018

7

PLL1 charge pump tristate

Tristates the PLL1 charge pump.

[6:0]

PLL1 charge pump control

These bits set the magnitude of the PLL1 charge pump current. Granularity is ~0.5 µA

with a full-scale magnitude of ~63.5 µA.

0x019

[7:5]

Reserved

Reserved.

4

Enable SPI control of antibacklash

pulse width

Setting this bit allows user control of the antibacklash pulse width setting in

Register 0x019[3:2].

0 (default): antibacklash period is forced to high.

1: antibacklash period defined by Register 0x019[3:2].

[3:2]

Antibacklash pulse width control

Controls the PFD antibacklash period. These bits default to the high setting unless

reprogrammed using Register 0x019[4] = 1b. The high setting decreases the

maximum allowable PLL1 PFD rate. See Table 7 for ranges.

00: minimum.

01: low.

10: high (initial state unless changed via Register 0x019[4] = 1b).

11: maximum.

[1:0]

PLL1 charge pump mode

Controls the mode of the PLL1 charge pump.

00 (default): tristate.

01: pump up.

10: pump down.

11: normal.

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