AD9523 datasheet(45/60 Pages) AD

Part #	AD9523

Description	Jitter Cleaner and Clock Generator

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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45 / 60 page

Data Sheet

AD9523

Rev. D | Page 45 of 60

Addr

(Hex)

Register

Name

(MSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

Bit 0

Default

Value

(Hex)

0x19F

Channel 5

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x20

0x1A0

10-bit channel divider[7:0] (LSB)

0x1F

0x1A1

Divider phase[5:0]

10-bit channel divider[9:8] (MSB)

0x04

0x1A2

Channel 6

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x00

0x1A3

10-bit channel divider[7:0] (LSB)

0x1F

0x1A4

Divider phase[5:0]

10-bit channel divider[9:8] (MSB)

0x04

0x1A5

Channel 7

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x20

0x1A6

10-bit channel divider[7:0] (LSB)

0x1F

0x1A7

Divider phase[5:0]

10-bit channel divider[9:8] (MSB)

0x04

0x1A8

Channel 8

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x00

0x1A9

10-bit channel divider[7:0] (LSB)

0x1F

0x1AA

Divider phase[5:0]

10-bit channel divider[9:8] (MSB)

0x04

0x1AB

Channel 9

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x20

0x1AC

10-bit channel divider[7:0] (LSB)

0x1F

0x1AD

Divider phase[5:0]

10-bit channel divider[9:8] (MSB)

0x04

0x1AE

Channel 10

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x00

0x1AF

10-bit channel divider[7:0] (LSB)

0x1F

0x1B0

Divider phase[5:0]

10-bit channel divider[9:8] (MSB)

0x04

0x1B1

Channel 11

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x20

0x1B2

10-bit channel divider[7:0] (LSB)

0x1F

0x1B3

Divider phase[5:0]

10-bit channel divider[9:8] (MSB)

0x04

0x1B4

Channel 12

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x00

0x1B5

10-bit channel divider[7:0] (LSB)

0x1F

0x1B6

Divider phase[5:0]

10-bit channel divider[9:8] (MSB)

0x04

0x1B7

Channel 13

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x20

0x1B8

10-bit channel divider[7:0] (LSB)

0x1F

0x1B9

Divider phase[5:0]

10-bit channel divider[9:8] (MSB)

0x04

0x1BA

PLL1 output

control

Reserved

PLL1 output

CMOS driver

strength

Out PLL1 output

0x00

0x1BB

PLL1 output

channel

control

PLL1

output

driver

power-

down

Reserved

Route

VCXO

clock to

Ch 3

divider

input

Route

VCXO

clock to

Ch 2

divider

input

Route VCXO

clock to Ch 1

divider input

Route VCXO

clock to Ch 0

divider input

0x80

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