ADCLK946

Data Sheet

Rev. B | Page 10 of 12

PCB LAYOUT CONSIDERATIONS

The ADCLK946 buffer is designed for very high speed

applications. Consequently, high speed design techniques must

be used to achieve the specified performance. It is critically

important to use low impedance supply planes for both the

part of a multilayer board. Providing the lowest inductance

return path for switching currents ensures the best possible

performance in the target application.

The following references to the ground plane assume that

the ground plane.

It is also important to adequately bypass the input and output

supplies. Place a 1 µF electrolytic bypass capacitor within several

addition, place multiple high quality 0.001 µF bypass capacitors

the capacitors to the ground plane with redundant vias.

Carefully select high frequency bypass capacitors for minimum

inductance and ESR. To improve the effectiveness of the bypass

at high frequencies, minimize parasitic layout inductance. Also,

avoid discontinuities along input and output transmission lines

that can affect jitter performance.

In a 50 Ω environment, input and output matching have a

significant impact on performance. The buffer provides internal

50 Ω termination resistors for both CLK and CLK inputs.

Normally, the return side is connected to the reference pin that is

provided. Carefully bypass the termination potential using

ceramic capacitors to prevent undesired aberrations on the

input signal due to parasitic inductance in the termination

return path. If the inputs are dc-coupled to a source, take care to

ensure that the pins are within the rated input differential and

common-mode ranges.

If the return is floated, the device exhibits a 100 Ω cross-

termination, but the source must then control the common-

mode voltage and supply the input bias currents.

There are ESD/clamp diodes between the input pins to prevent

the application from developing excessive offsets to the input

transistors. ESD diodes are not optimized for best ac perfor-

mance. When a clamp is required, it is recommended that

appropriate external diodes be used.

Exposed Metal Paddle

The exposed metal paddle on the ADCLK946 package is both

an electrical connection and a thermal enhancement. For the

device to function properly, the paddle must be properly

When properly mounted, the ADCLK946 also dissipates heat

through its exposed paddle. The PCB acts as a heat sink for the

ADCLK946. The PCB attachment must provide a good thermal

path to a larger heat dissipation area. This requires a grid of vias

The ADCLK946 evaluation board (ADCLK946/PCBZ)

provides an example of how to attach the part to the PCB.

PLANE

Figure 18. PCB Land for Attaching Exposed Paddle