ADCLK946_17 datasheet(6/12 Pages) AD

Part #	ADCLK946

Description	Six LVPECL Outputs, SiGe Clock Fanout Buffer

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Manufacturer	AD [Analog Devices]

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ADCLK946

Data Sheet

Rev. B | Page 6 of 12

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VEE

CLK

VREF

VT

VEE

Q3

Q2

VCC

Q3

VCC

NOTES

1. EXPOSED PADDLE MUST BE CONNECTED TO VEE.

2

1

3

4

5

6

18

17

16

15

14

13

ADCLK946

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 6, 7, 12, 19

VEE

Negative Supply Pin.

2

CLK

Differential Input (Positive).

3

CLK

Differential Input (Negative).

4

VREF

Reference Voltage. This pin provides the reference voltage for biasing ac-coupled CLK and CLK inputs.

5

VT

Center Tap. This pin provides the center tap of a 100 Ω input resistor for CLK and CLK inputs.

8, 9

Q5, Q5

Differential LVPECL Outputs.

10, 11

Q4, Q4

Differential LVPECL Outputs.

13, 18, 24

VCC

Positive Supply Pin.

14, 15

Q3, Q3

Differential LVPECL Outputs.

16, 17

Q2, Q2

Differential LVPECL Outputs.

20, 21

Q1, Q1

Differential LVPECL Outputs.

22, 23

Q0, Q0

Differential LVPECL Outputs.

EPAD

EPAD must be soldered to VEE.

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