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M29W160DB Datasheet(PDF) 17 Page - STMicroelectronics |
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M29W160DB Datasheet(HTML) 17 Page - STMicroelectronics |
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17 / 42 page  17/42 M29W160DT, M29W160DB Table 6. Program, Erase Times and Program, Erase Endurance Cycles Note: 1. TA =25°C, VCC = 3.3V. STATUS REGISTER Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Sus- pend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 7, Status Register Bits. Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its opera- tion or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being pro- grammed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the ad- dress just programmed output DQ7, not its com- plement. During Erase operations the Data Polling Bit out- puts ’0’, the complement of the erased state of DQ7. After successful completion of the Erase op- eration the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/Erase Controller has suspended the Erase operation. Figure 8, Data Polling Flowchart, gives an exam- ple of how to use the Data Polling Bit. A Valid Ad- dress is the address being programmed or an address within the block being erased. Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has re- sponded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with succes- sive Bus Read operations at any address. After successful completion of the operation the memo- ry returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. If any attempt is made to erase a protected block, the operation is aborted, no error is signalled and DQ6 toggles for approximately 100 µs. If any at- tempt is made to program a protected block or a suspended block, the operation is aborted, no er- ror is signalled and DQ6 toggles for approximately 1 µs. Figure 9, Data Toggle Flowchart, gives an exam- ple of how to use the Data Toggle Bit. Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to ’1’ when a Pro- gram, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do so will set DQ5 to ‘1’. A Bus Read operation to that ad- dress will show the bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’ Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase com- mand. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Parameter Min Typ (1) Typical after 100k W/E Cycles (1) Max Unit Chip Erase 29 34 120 s Block Erase (64 Kbytes) 0.8 6 s Program (Byte or Word) 13 14 200 µs Chip Program (Byte by Byte) 26 28 120 s Chip Program (Word by Word) 13 14 60 s Program/Erase Cycles (per Block) 100,000 cycles |
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