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APD-128G064A Datasheet(PDF) 1 Page - Vishay Siliconix |
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APD-128G064A Datasheet(HTML) 1 Page - Vishay Siliconix |
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1 / 1 page ![]() Document Number: 37009 Revision 08-Nov-00 www.vishay.com 2 APD-128G064A Vishay Dale Plasma Display Modules 128 x 64 Graphics Display with Drive Electronics and TTL Level Data Interface FEATURES • TTL level video interface • Slim profile • Highly visible for long distance viewing • Large bright characters • High contrast ELECTRICAL SPECIFICATIONS Power Required: Typical = 12 watts. Maximum = 35 watts. Maximum Current Requirements: Icc (Vcc logic) - 0.050 Amps. Isp (Column driver supply) - 0.192 Amps. Isn (Row driver supply) - 0.192 Amps. Irw (Row driver logic) - 0.010 Amps. OPTICAL SPECIFICATIONS Viewing Area: 12.75" [323.85mm] W x 6.35" [161.29mm] L Character Array: 21 characters per line, 8 lines of characters. Character Size: 0.65" [16.51mm] H x 0.45" [11.43mm] W. Pixel Size: 0.050" [1.27mm] square. Pixel Pitch: 0.100" [2.54mm]. Luminance: 50 foot lamberts minimum. Contrast Ratio: > 20:1. The APD-128G064A DC plasma display offers viewing qualities designers seek such as high contrast, viewing angle of 150 ° minimum and excellent readability. Its bright (50 foot lambert minimum) with characters and graphics figures presented in a pleasing neon orange color against a black background. Plasma is much more readable and eye-pleasing than liquid crystal or vacuum fluorescent displays and is filterable to red, amber or neutral density. These plasma display panels are driven in a standard row-column refresh method much like a CRT display. The designer need only supply TTL level signals for SERIAL DATA, DOT CLOCK, COLUMN LATCH, ROW DATA, ROW CLOCK and DISPLAY ENABLE. The SERIAL DATA is entered with the DOT CLOCK up to frequencies as high as 8mHz. After a row of 128 pixels is clocked in, the COLUMN LATCH signal is toggled and the data is latched. At the time the data is latched, the display is briefly disabled using the DISPLAY ENABLE signal, then the row pointer is advanced with the ROW CLOCK signal. Once each frame the ROW DATA must be asserted to synchronize the column serial data with the beginning row. The recommended scanning frequency is approximately 70 Hz, but may be as high as 200 Hz. The high clock rate on the data clock allows for rapid refresh and maximum access time to the refresh ram. *Recommended operating voltages. All maximums are to be considered absolute maximum. **V rw is referenced to Vsn. DESCRIPTION PART NUMBER Display Module with Drivers and TTL Interface ............................................................................................. APD-128G064A Display Module with Drivers, TTL Interface and On Board DC Converter ................................................. APD-128G064A-1 Data Connector Kit ................................................................................................................................................. 280105-05 Power Connector Kit .............................................................................................................................................. 280108-12 ORDERING INFORMATION DIMENSIONS in inches [millimeters] Pin #1 of P1 .450 [11.43] Max. .487 [12.37] 8.125 [206.38] 128 x 64 Full Field 13.775 [349.88] 12.75 [323.85] 7.40 [187.96] 14.50 [368.30] Column 1, Row 1 7.825 [198.76] 7.275 [184.78] 6.35 [161.29] 4.062 [103.17] .150 [3.81] Center of Display Area 7.25 [184.15] .888 [22.56] .150 [3.81] .447 ± .020 [11.35 ± .508] 14.80 [375.92] 1.025 [26.04] Pin #1 of P2 7.40 [187.96] C L C L C L 10.50 [266.70] 4.15 [105.41] .062 [1.575] PCB Thickness STANDARD ELECTRICAL SPECIFICATIONS* DESCRIPTION Logic Supply Anode Supply Cathode Supply Cathode Control** Total + Vsp & - Vsn Logic 1 Input Logic 0 Input SYMBOL Vcc Vsp Vsn Vrw Vtot Vih Vil MIN. + 4.5 — — + 10.8 170 2.0 — TYP. + 5.0 + 75 - 110 + 12.0 185 — — MAX. + 5.5 + 80 - 125 + 15.0 205 — 0.8 UNITS VDC VDC VDC VDC VDC VDC VDC |
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