1:10 Differential LVPECL/LVECL/HSTL

Clock and Data Drivers

8

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differential pair by matching the electrical length of the

traces.

Output Termination

Terminate outputs through 50

equivalent Thevenin termination. When a single-ended

signal is taken from a differential output, terminate both

outputs. For example, if Q0 is used as a single-ended

output, terminate both Q0 and Q0.

Chip Information

TRANSISTOR COUNT: 250

Q_

Q_

CLK_

CLK_

Figure 1. Switching with Single-Ended Input

0 (DIFFERENTIAL)

80%

20%

80%

20%

0 (DIFFERENTIAL)

Q_

Q_

(Q_) - (Q_)

CLK_

CLK_

Figure 2. Differential Transition Time and Propagation Delay Timing Diagram