LTC6752 datasheet(20/30 Pages) AD

Part #	LTC6752

Description	Comparator Family with Rail-to-Rail Inputs

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Manufacturer	AD [Analog Devices]

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LTC6752/LTC6752-1/

LTC6752-2/LTC6752-3/

LTC6752-4

20

6752fc

For more information www.linear.com/LTC6752

applicaTions inForMaTion

Latching

TheinternallatchoftheLTC6752-1/LTC6752-2/LTC6752-3

retains the output state when the LE/HYST pin is taken to

less than 300mV above the negative supply.

Figures 7a to 7e illustrate the latch timing definitions. The

latch setup time is defined as the time for which the input

should be stable before the latch pin is asserted low to

ensure that the correct state will be held at the output. The

latch hold time is the interval after which the latch pin is

asserted in which the input signal must remain stable for

the output to be the correct state at the time latch was

asserted. The latch to output delay (tPL) is the time taken

for the output to return to input control after the latch

pin is released. Latching is disabled if the LE/HYST pin

is left floating. Both outputs of the LTC6752-3 are latch

controlled simultaneously.

6752 F07a

+IN – –IN

t > tSETUP

tPD

Q

LE/HYST

6752 F07d

+IN – –IN

t > tHOLD

tPD

Q

LE/HYST

t > tSETUP

6752 F07e

+IN – –IN

tPL

Q

LE/HYST

6752 F07c

+IN – –IN

t < tHOLD

tPD

Q

LE/HYST

6752 F07b

+IN – –IN

t < tSETUP

Q

LE/HYST

Figure 7a. Input State Change Properly Latched

Figure 7b. Input Change Setup Time Too Short

Figure 7c. Input State Not Held Long Enough.

Wrong Output State Latched

Figure 7d. Short Input Pulse Properly

Captured and Latched

Figure 7e. Latched Output Disabled

Shutdown

The LTC6752-2 and LTC6752-3 have shutdown pins

(SHDN, active low) that can reduce the total supply cur-

rent to a typical value of 580μA for the LTC6752-2 and

650µA for the LTC6752-3 (2.5V supply). When the part is

in shutdown, the outputs are placed in a high-impedance

state,sincePFETandNFEToutputtransistorswhosedrains

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