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AT25020A-10PQ-2.7 Datasheet(PDF) 5 Page - ATMEL Corporation |
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AT25020A-10PQ-2.7 Datasheet(HTML) 5 Page - ATMEL Corporation |
5 / 18 page ![]() 5 AT25010A/020A/040A 5087B–SEEPR–1/05 Serial Interface Description MASTER: The device that generates the serial clock. SL AVE: B e c a us e t h e s e ri a l c l oc k pi n (S CK ) i s al w a y s an i n p u t , t h e AT25010A/020A/040A always operates as a slave. TRANSMITTER/RECEIVER: The AT25010A/020A/040A has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. The op-code also contains address bit A8 in both the Read and Write instructions. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25010A/020A/040A, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25010A/020A/040A is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HO L D : T he HOLD pi n i s used i n conj un cti on wit h the CS pi n to s e le ct th e AT25010A/020A/040A. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low, all write operations are inhibited. WP going low while CS is still low will interrupt a write to the AT25010A/020A/040A. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation. |
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