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LTC2220 Datasheet(PDF) 24 Page - Linear Technology |
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LTC2220 Datasheet(HTML) 24 Page - Linear Technology |
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24 / 32 page  LTC2220/LTC2221 24 22201fa As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2220/LTC2221 should drive a minimal capacitive load to avoid possible interaction be- tween the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. Lower OVDD voltages will also help reduce interference from the digital outputs. Digital Output Buffers (LVDS Mode) Figure 13b shows an equivalent circuit for a differential output pair in the LVDS output mode. A 3.5mA current is steered from OUT+ to OUT– or vice versa which creates a ±350mV differential voltage across the 100Ω termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.25V. For proper operation each LVDS output pair needs an external 100 Ω termination resistor, even if the signal is not used (such as OF+/OF– or CLKOUT+/CLKOUT–). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length. APPLICATIO S I FOR ATIO Table 3. MODE Pin Function Clock Duty MODE Pin Output Format Cycle Stablizer 0 Offset Binary Off 1/3VDD Offset Binary On 2/3VDD 2’s Complement On VDD 2’s Complement Off Data Format The LTC2220/LTC2221 parallel digital output can be se- lected for offset binary or 2’s complement format. The format is selected with the MODE pin. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2’s comple- ment output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 3 shows the logic states for the MODE pin. LTC2220/LTC2221 22201 F13b OVDD LVDS RECEIVER OGND 1.25V D D D D OUT+ OUT– 100 Ω + – 3.5mA 10k 10k Figure 13b. Digital Output in LVDS Mode Overflow Bit An overflow output bit indicates when the converter is overranged or underranged. In CMOS mode, a logic high on the OFA pin indicates an overflow or underflow on the A data bus, while a logic high on the OFB pin indicates an overflow or underflow on the B data bus. In LVDS mode, a differential logic high on the OF+/OF– pins indicates an overflow or underflow. Output Clock The ADC has a delayed version of the ENC+ input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. In all CMOS modes, A bus data will be updated just after CLKOUTA rises and can be latched on the falling edge of CLKOUTA. In demux CMOS mode with interleaved update, B bus data will be updated just after CLKOUTB rises and can be latched on the falling edge of CLKOUTB. In demux CMOS mode with si- multaneous update, B bus data will be updated just after CLKOUTB falls and can be latched on the rising edge of CLKOUTB. In LVDS mode, data will be updated just after CLKOUT+/CLKOUT– rises and can be latched on the falling edge of CLKOUT+/CLKOUT–. |
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Similar Description - LTC2220 |
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