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LTC2220 Datasheet(PDF) 20 Page - Linear Technology |
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LTC2220 Datasheet(HTML) 20 Page - Linear Technology |
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20 / 32 page  LTC2220/LTC2221 20 22201fa the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.6V. The VCM output pin (Pin 60) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2 µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2220/LTC2221 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC, the sample-and-hold circuit will connect the 1.6pF sam- pling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100 Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2220/LTC2221 being driven by an RF transformer with a center tapped secondary. The sec- ondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio trans- former. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100 Ωforeach ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transform- ers have poor performance at frequencies below 1MHz. Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequencyinputresponse;however,thelimitedgainbandwidth of most op amps will limit the SFDR at high input frequencies. Figure 5 shows a single-ended input circuit. The imped- ance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25 Ωresistorsand12pFcapacitorontheanaloginputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequen- cies higher than 100MHz, the capacitor may need to be decreased to prevent excessive signal loss. 25 Ω 25 Ω 25 Ω 25 Ω 0.1 µF AIN + AIN + AIN – AIN – 12pF 2.2 µF VCM LTC2220/ LTC2221 ANALOG INPUT 0.1 µFT1 1:1 T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 22201 F03 Figure 3. Single-Ended to Differential Conversion Using a Transformer 25 Ω 25 Ω AIN + AIN + AIN – AIN – 12pF 2.2 µF 3pF 3pF VCM LTC2220/ LTC2221 22201 F04 – – + + CM ANALOG INPUT HIGH SPEED DIFFERENTIAL AMPLIFIER AMPLIFIER = LTC6600-20, LT1993, ETC. Figure 4. Differential Drive with an Amplifier APPLICATIO S I FOR ATIO Figure 5. Single-Ended Drive 25 Ω 0.1 µF ANALOG INPUT VCM AIN + AIN + AIN – AIN – 1k 12pF 22201 F05 2.2 µF 1k 25 Ω 0.1 µF LTC2220/ LTC2221 |
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Similar Description - LTC2220 |
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