IS61LV6432

4

Integrated Circuit Solution Inc.

SSR005-0B

TRUTH TABLE

Address

Operation

Used

CE1

CE1

CE1

CE1

CE1

CE2

CE3

CE3

CE3

CE3

CE3

ADSP

ADSP

ADSP

ADSP

ADSP ADSC

ADSC

ADSC

ADSC

ADSC ADV

ADV

ADV

ADV

ADV WRITE

WRITE

WRITE

WRITE

WRITE

OE

OE

OE

OE

OE

DQ

Deselected, Power-down

None

H

X

X

X

L

X

X

X

High-Z

Deselected, Power-down

None

L

L

X

L

XXXX

High-Z

Deselected, Power-down

None

L

X

H

L

XXXX

High-Z

Deselected, Power-down

None

L

L

X

H

L

X

X

X

High-Z

Deselected, Power-down

None

L

X

H

H

L

X

X

X

High-Z

Read Cycle, Begin Burst

External

L

H

L

L

X

X

X

L

Q

Read Cycle, Begin Burst

External

L

H

L

L

X

X

X

H

High-Z

Write Cycle, Begin Burst

External

L

H

L

H

L

X

L

X

D

Read Cycle, Begin Burst

External

L

H

L

H

L

X

H

L

Q

Read Cycle, Begin Burst

External

L

H

L

H

L

X

H

H

High-Z

Read Cycle, Continue Burst

Next

X

X

X

H

H

L

H

L

Q

Read Cycle, Continue Burst

Next

X

X

X

H

H

L

H

H

High-Z

Read Cycle, Continue Burst

Next

H

X

X

X

H

L

H

L

Q

Read Cycle, Continue Burst

Next

H

X

X

X

H

L

H

H

High-Z

Write Cycle, Continue Burst

Next

X

X

X

H

H

L

L

X

D

Write Cycle, Continue Burst

Next

H

X

X

X

H

L

L

X

D

Read Cycle, Suspend Burst

Current

X

X

X

HHHH

L

Q

Read Cycle, Suspend Burst

Current

X

X

X

HHHHH

High-Z

Read Cycle, Suspend Burst

Current

H

X

X

X

H

H

H

L

Q

Read Cycle, Suspend Burst

Current

H

X

X

X

HHHH

High-Z

Write Cycle, Suspend Burst

Current

X

X

X

H

H

H

L

X

D

Write Cycle, Suspend Burst

Current

H

X

X

X

H

H

L

X

D

Notes:

1. All inputs except

OE must meet setup and hold times for the Low-to-High transition of clock (CLK).

2. Wait states are inserted by suspending burst.

3. X means don't care.

WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is

LOW.

WRITE=H means all byte write enable signals are HIGH.

4. For a Write operation following a Read operation,

OE must be HIGH before the input data required setup time and held

HIGH throughout the input data hold time.

5.

ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or

more byte write enable signals and

BWE LOW or GW LOW for the subsequent L-H edge of clock.

PARTIAL TRUTH TABLE

Function

GW

GW

GW

GW

GW

BWE

BWE

BWE

BWE

BWE

BW1

BW1

BW1

BW1

BW1

BW2

BW2

BW2

BW2

BW2

BW3

BW3

BW3

BW3

BW3 BW4

BW4

BW4

BW4

BW4

READ

H

H

X

X

X

X

READ

H

X

H

H

H

H

WRITE Byte 1

H

L

L

H

H

H

WRITE All Bytes

X

LLLL

L

WRITE All Bytes

L

XXXX

X