S1D2512X01

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

31

A negative or positive TTL level pulse applied on pin 2 (VSYNC) as well as a TTL composite sync on pin 1 can

Synchronize the ramp in the range [fmin, fmax]. This frequency range depends on the external capacitor

connected on pin 22. A capacitor in the range [150nF,

± 5%] is recommended for application in the following range:

50Hz to 185Hz.

Typical maximum and minimum frequency, at 25

°C and without any correction (S correction or C correction), can

be calculated by:

If S or C corrections are applied, these values are slightly affected.

If a Synchronization pulse is applied, the internal oscillator is synchronized immediately but the amplitude changes.

An internal correction is activated to adjust it in less than a half a second: the highest voltage of the ramp pin 22 is

sampled on the sampling capacitor connected on pin 20 at each clock pulse and a transconductance amplifier

generates the charge current of the capacitor. The ramp amplitude becomes again constant.

The read status register enables to have the vertical lock-unlock and the vertical sync polarity informations.

It is recommended to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory.

A good stability of the internal closed loop is reached by a 470nF

± 5% capacitor value on pin 20 (VAGC)

Figure 13. AGC Loop Block Diagram

2

SYNCHRO

OSCILLATOR

20

-

+

22

Switch

Disch

23

V-SYNC

POLARITY

DISCH.

OSC

CAP

CHARGE CURRENT

TRANSCONDUCTANCE

AMPLIFIER

REF

SAMP

CAP

SAMPLING

S CORRECTION

VS_AMP

SUB07/6bits

COR-C

SUB08/6bits

C CORRECTION

Vlow

18

VERT_AMP

SUB05/7BITS

VMOIRE

SUB0C/5BITS

VOSITION

SUB06/7BITS

BREATH

-

+

VOUT