S1D2512X01

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

27

The S1D2512X01 also includes a lock/unlock identification block which senses in real time whether PLL1 is locked

or not on the incoming horizontal sync signal. The resulting information is available on Hlockout (see sync

processor). The block function is described in figure 5.

When PLL1 is unlocked, It forces Hlockout to leave high.

PLL2

The PLL2 ensures a constant position of the shaped Flyback signal in comparison with the sawtooth of the VCO

(Figure 8). The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output

current:0.5mA). The Flyback input is composed of an NPN transistor. This input must be current driven. The

maximum recommended input current is 5mA (see Figure 9).

power on reset) is 60% in order to avoid having a too long conduction period of the horizontal scanning transistor.

Figure 8. PLL2 Timing Diagram

Figure 9. Flyback Input Electrical Diagram

H osc

Sawtooth

6.4V

4.0V

1.6V

Shaped Flyback

H drive

Flyback

Internally

Duty Cycle

Ts

12

HFLY

400

Ω

20K

Ω

Q1

GND 0V