S1D2512X01

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

25

PLL1

The PLL1 is composed of a phase comparator, an external filter and a voltage control oscillator (VCO).

The phase comparator is a phase frequency type designed in CMOS technology. This kind of phase detector

avoids locking on wrong frequencies. It is followed by a charge pump, composed of two current sources sunk and

sourced (I = 1mA typ. when locked, I = 140

µA when unlocked). This difference between lock/unlock permits a

smooth catching of horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system

when PLL1 is locked avoiding horizontal too fast frequency change.

The dynamic behavior of the PLL is fixed by an external filter which integrates the current of the charge pump.

A CRC filter is generally used (see Figure 4)

PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong

pulse on phase comparator. The inhibition results from the opening of a switch located between the charge pump

and the filter (see Figure 5).

The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and discharge of the

capacitor, by a current proportional to the current in the resistor. Typical thresholds of sawtooth are 1.6V and 6.4V.

Figure 4. PLL1

Figure 5. Block Diagram

7

PLL1F

1.8K

Ω

4.7uF

1uF

Input

Interface

Comp1

Charge

PUMP

PLL

Inhibition

VCO

7

6

5

Lockdet

3

Phase

Adjust

OSC

Hpos

Adj.

Low

High

E2

Tramext

HSYNC

H-LOCKOUT

Lock/Unlock

Status

Tramext

Forced

Frequency

PLL1F R0

C0

1