6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

15

Timing Waveform of Write with BUSY

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

Waveform of BUSY Arbitration Cycle Controlled by Address Match

NOTES:

BUSY input (slave) and output (master).

2.

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R/

R/

(1)

(2)

(3)

,

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ADDRESSES MATCH

(2)

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ADDRESS "N"

(2)

MATCHING ADDRESS "N"