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IDT70V05L20PFI Datasheet(PDF) 12 Page - Integrated Device Technology |
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IDT70V05L20PFI Datasheet(HTML) 12 Page - Integrated Device Technology |
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12 / 22 page  6.42 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges 12 Timing Waveform of Semaphore Read after Write Timing, Either Side(1) NOTE: 1. CE = VIH for the duration of the above timing (both write and read cycle). 2. “DATAOUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) SEM"A" 2941 drw 11 tSPS MATCH R/ W"A" MATCH A0"A"-A2"A" SIDE "A" (2) SEM"B" R/ W"B" A0"B"-A2"B" SIDE "B" (2) NOTES: 1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. “A” may be either left or right port. “B” is the opposite port from “A”. 3. This parameter is measured from R/ W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH. 4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag. SEM 2941 drw 10 tAW tEW tSOP DATA0 VALID ADDRESS tSAA R/ W tWR tOH ttACE VALID ADDRESS DATAIN VALID DATA OUT tDW tWP tDH tAS tSWRD tAOE tSOP Read Cycle Write Cycle A0-A2 OE VALID(2) |
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