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IDT70V05L20PFI Datasheet(PDF) 18 Page - Integrated Device Technology |
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IDT70V05L20PFI Datasheet(HTML) 18 Page - Integrated Device Technology |
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18 / 22 page  6.42 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges 18 Truth Table IV Address BUSY Arbitration NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V05 are push pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes. 2. VIL if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be low simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin. Truth Table V Example of Semaphore Procurement Sequence(1,2,3) NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V05. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2. 3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. Truth Table III Interrupt Flag(1) NOTES: 1. Assumes BUSYL = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. Left Port Right Port Function R/ WL CEL OEL A12L-A0L INTL R/ WR CER OER A12R-A0R INTR LL X 1FFF X X X X X L(2) Set Right INTR Flag X X XXX X L L 1FFF H (3) Reset Right INTR Flag XX X X L (3) L L X 1FFE X Set Left INTL Flag XL L 1FFE H(2) X X X X X Reset Left INTL Flag 2941tbl 15 Inputs Outputs Function CEL CER A12L-A0L A12R-A0R BUSYL(1) BUSYR(1) X X NO MATCH HHNormal H X MATCH HHNormal X H MATCH HHNormal L L MATCH (2) (2) Write Inhibit(3) 2941 tbl 16 Functions D0 - D7 Left D0 - D7 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free 2941 tbl 17 |
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