+

–

+

–

+

–

+

+

SDZ

MUTE

TTL

Buffer

Gain

Control

GAIN

OUTPR_FB

RINP

RINN

Gain

Control

OUTPNR_FB

FAULTZ

SYNC

GAIN/SLV

AM<2:0>

PLIMIT

AVCC

GVDD

LDO

Regulator

LINP

LINN

GND

Input

Sense

PBTL

Select

OUTPL_FB

Gain

Control

OUTNL_FB

AVDD

GVDD

PLIMIT

Reference

Ramp

Generator

Biases and

References

Startup Protection

Logic

SC Detect

DC Detect

Thermal

Detect

UVLO/OVLO

PVCC

GVDD

PVCC

Gate

Drive

OUTNL_

FB

PVCC

GVDD

PVCC

Gate

Drive

PWM

Logic

Modulation and

PBTL Select

OUTPL_FB

GND

OUTPL

BSPL

GND

OUTNL

BSNL

GND

BSNR

OUTPR

GND

OUTNR

OUTNR_

FB

BSPR

OUTPR_FB

PVCC

GVDD

PVCC

Gate

Drive

PVCC

GVDD

PVCC

Gate

Drive

PWM

Logic

Modulation and

PBTL Select

PLIMIT

PLIMIT

+

–

+

–

+

–

+

–

+

–

+

–

–

–

Thermal

Pad

+

–

PVCC

PVCC

Input

Sense

MONO

Select

13

TPA3126D2

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SLOS942 – APRIL 2018

Product Folder Links: TPA3126D2

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Copyright © 2018, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The analog-input Class-D amplifier TPA3126D2 is a performance upgrade to the prior generation TPA3116D2. It

features a more efficient, 90-mΩ MOSFET, and has an extremely-low idle current of < 23 mA (24 V) in the

standard LC filter configuration. The device can operate from the ultra-low-idle-loss modulation scheme, which

enables low power dissipation in both idle condition and while playing music, optimized for battery-powered audio

systems.

The TPA3126D2 supports both stereo and mono BTL modes, as well as mono PBTL mode. Comparing to the

conventional Class-D amplifiers, in the mono BTL mode, the idle channel of the TPA3126D2 is not in the

switching mode; therefore, it saves nearly half of the power loss, enabling low-power operation in single channel

applications.

The device may be configured for either master or slave operation by using the SYNC pin. This configuration

helps prevent the audible beats noise.

8.2 Functional Block Diagram