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TPA3126D2 Datasheet(PDF) 5 Page - Texas Instruments |
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TPA3126D2 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 38 page  5 TPA3126D2 www.ti.com SLOS942 – APRIL 2018 Product Folder Links: TPA3126D2 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE(1) DESCRIPTION NO. NAME 10 LINP I Positive audio input for left channel. Connect to GND for PBTL mode. 11 LINN I Negative audio input for left channel. Connect to GND for PBTL mode. 12 MUTE I Mute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC. 13 AM2 I AM Avoidance Frequency Selection 14 AM1 I AM Avoidance Frequency Selection 15 AM0 I AM Avoidance Frequency Selection 16 SYNC DIO Clock input/output for synchronizing multiple Class-D devices. Direction determined by GAIN/SLV terminal. Refer to: Gain Setting and Master and Slave 17 AVCC P Analog Supply 18 PVCC P Power supply 19 PVCC P Power supply 20 BSNL BST Boot strap for negative left channel output, connect to 220 nF X5R, or better ceramic cap to OUTPL 21 OUTNL PO Negative left channel output 22 GND G Ground 23 OUTPL PO Positive left channel output 24 BSPL BST Boot strap for positive left channel output, connect to 220 nF X5R, or better ceramic cap to OUTNL Refer to: BSPx and BSNx Capacitors 25 GND G Ground 26 BSNR BST Boot strap for negative right channel output, connect to 220 nF X5R, or better ceramic cap to OUTNR. Refer to: BSPx and BSNx Capacitors 27 OUTNR PO Negative right channel output 28 GND G Ground 29 OUTPR PO Positive right channel output 30 BSPR BST Boot strap for positive right channel output, connect to 220 nF X5R or better ceramic cap to OUTPR. Refer to: BSPx and BSNx Capacitors 31 PVCC P Power supply 32 PVCC P Power supply PowerPAD™ G Connect to GND for best system performance. If not connected to GND, leave floating. |
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