Input

Signal

IN

15

TPA3126D2

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SLOS942 – APRIL 2018

Product Folder Links: TPA3126D2

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Table 2. Recommended Input AC-Coupling Capacitors

GAIN

INPUT IMPEDANCE

INPUT CAPACITANCE

HIGH-PASS FILTER

20 dB

50 kΩ

1.5 µF

2.1 Hz

26 dB

25 kΩ

3.3 µF

1.9 Hz

32 dB

12.5 kΩ

5.6 µF

2.3 Hz

36 dB

7.3 kΩ

10 µF

2.2 Hz

Figure 26. Input Impedance

The input capacitors should be a type of low leakage, such as quality electrolytic, tantalum, or ceramic

capacitors. If a polarized type is used the positive connection should face the input pins which are biased to 3

Vdc.

8.3.3 Startup and Shutdown Operation

minimum level during periods of non-use for power conservation. The SDZ input terminal should be held high

(see specification table for trip point) during normal operation when the amplifier is in use. Pulling SDZ low puts

the outputs to mute and the amplifier to enter a low-current state. Do not leave SDZ unconnected, because the

amplifier operation is unpredictable.

For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power

supply. The gain setting is selected at the end of the start-up cycle, and cannot be changed until the next power-

up.

8.3.4 PLIMIT Operation

The TPA3126D2 has a built-in voltage limiter that can be used to limit the output voltage level below the supply

rail. The amplifier operates as if it was powered by a lower supply voltage, and thereby, limits the output power.

Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also

be used if tighter tolerance is required. Add a 1-µF capacitor from pin PLIMIT to ground to ensure stability.

Figure 27. Power Limit Example