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CY7C1461KV33 Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY7C1461KV33 Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 23 page  CY7C1461KV33 CY7C1463KV33 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-66681 Rev. *G Revised June 7, 2016 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture Features ■ No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133 MHz bus operations with zero wait states ❐ Data is transferred on every clock ■ Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.3 V and 2.5 V I/O power supply ■ Fast clock-to-output times ❐ 6.5 ns (for 133-MHz device) ■ Clock Enable (CEN) pin to enable clock and suspend operation ■ Synchronous self timed writes ■ Asynchronous Output Enable ■ CY7C1461KV33, CY7C1463KV33 available in JEDEC-standard Pb-free 100-pin TQFP packages ■ Three chip enables for simple depth expansion ■ Automatic power down feature available using ZZ mode or CE deselect ■ Burst capability – linear or interleaved burst order ■ Low standby power Functional Description The CY7C1461KV33/CY7C1463KV33 are 3.3 V, 1M × 36/2M × 18 Synchronous Flow-Through Burst SRAMs designed specifically to support unlimited true back-to-back read and write operations without the insertion of wait states. The CY7C1461KV33/CY7C1463KV33 is equipped with the advanced NoBL logic required to enable consecutive read and write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133 MHz device). Write operations are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Selection Guide Description 133 MHz Unit Maximum access time 6.5 ns Maximum operating current × 18 150 mA × 36 170 |
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