CY7C1461KV33 datasheet(9/23 Pages) CYPRESS

Part #	CY7C1461KV33

Description	36-Mbit (1M 횞 36/2M 횞 18) Flow-Through SRAM with NoBL??Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY7C1461KV33

CY7C1463KV33

Document Number: 001-66681 Rev. *G

Page 9 of 23

Burst Write Accesses

The CY7C1461KV33/CY7C1463KV33 have an on-chip burst

counter that provides the ability to supply a single address and

conduct up to four write operations without reasserting the

address inputs. ADV/LD must be driven LOW to load the initial

address, as described in the Single Write Accesses section.

When ADV/LD is driven HIGH on the subsequent clock rise, the

chip enables (CE1, CE2, and CE3) and WE inputs are ignored

and the burst counter is incremented. The correct BWX inputs

must be driven in each cycle of the burst write, to write the correct

bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation sleep mode. Two clock cycles

are required to enter into or exit from this sleep mode. When in

this mode, data integrity is guaranteed. Accesses pending when

entering the sleep mode are not considered valid nor is the

completion of the operation guaranteed. The device must be

deselected prior to entering the sleep mode. CE1, CE2, and CE3,

must remain inactive for the duration of tZZREC after the ZZ input

returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Linear Burst Address Table

(MODE = GND)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min

Max

Unit

IDDZZ

Sleep mode standby current

ZZ > VDD– 0.2 V

–

75

mA

tZZS

Device operation to ZZ

ZZ > VDD – 0.2 V

–

2tCYC

ns

tZZREC

ZZ recovery time

ZZ < 0.2 V

2tCYC

–ns

tZZI

ZZ active to sleep current

This parameter is sampled

–

2tCYC

ns

tRZZI

ZZ Inactive to exit sleep current This parameter is sampled

0

–

ns

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