CY7C1441KV33 datasheet(15/32 Pages) CYPRESS

Part #	CY7C1441KV33

Description	36-Mbit (1M 횞 36/2M 횞 18) Flow-Through SRAM (With ECC)

PDF	32 Pages

Scroll/Zoom	100%

Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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15 / 32 page

CY7C1441KV33

CY7C1443KV33

CY7C1441KVE33

Document Number: 001-66677 Rev. *I

Page 15 of 32

3.3 V TAP AC Test Conditions

Input pulse levels ...............................................VSS to 3.3 V

Input rise and fall times (Slew Rate) ........................... 2 V/ns

Input timing reference levels ......................................... 1.5 V

Output reference levels ................................................ 1.5 V

Test load termination supply voltage ............................ 1.5 V

2.5 V TAP AC Test Conditions

Input pulse levels ...............................................VSS to 2.5 V

Input rise and fall times (Slew Rate) ........................... 2 V/ns

Input timing reference levels ................. ......................1.25 V

Output reference levels ................ ..............................1.25 V

Test load termination supply voltage .................. ........1.25 V

TAP AC Switching Characteristics

Over the Operating Range

Parameter [9, 10]

Description

Min

Max

Unit

Clock

tTCYC

TCK Clock Cycle Time

50

–

ns

tTF

TCK Clock Frequency

–

20

MHz

tTH

TCK Clock HIGH time

20

–

ns

tTL

TCK Clock LOW time

20

–

ns

Output Times

tTDOV

TCK Clock LOW to TDO Valid

–

10

ns

tTDOX

TCK Clock LOW to TDO Invalid

0

–

ns

Setup Times

tTMSS

TMS Setup to TCK Clock Rise

5

–

ns

tTDIS

TDI Setup to TCK Clock Rise

5

–

ns

tCS

Capture Setup to TCK Rise

5

–

ns

Hold Times

tTMSH

TMS Hold after TCK Clock Rise

5

–

ns

tTDIH

TDI Hold after Clock Rise

5

–

ns

tCH

Capture Hold after Clock Rise

5

–

ns

3.3 V TAP AC Output Load Equivalent

TDO

1.5V

20p F

Z

= 50

Ω

O

50

Ω

2.5 V TAP AC Output Load Equivalent

TDO

1.25V

20pF

Z = 50

Ω

O

50

Ω

Notes

9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 2 V/ns (Slew Rate).

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CY7C1441KV33 Datasheet(PDF) 15 Page - Cypress Semiconductor

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