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CY7C1441KV33 Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY7C1441KV33 Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 32 page  CY7C1441KV33 CY7C1443KV33 CY7C1441KVE33 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM (With ECC) Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-66677 Rev. *I Revised February 15, 2018 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM (With ECC) Features ■ Supports 133-MHz bus operations ■ 1M × 36/2M × 18 common I/O ■ 3.3 V core power supply ■ 2.5 V or 3.3 V I/O power supply ■ Fast clock-to-output times ❐ 6.5 ns (133 MHz version) ■ Provide high-performance 2-1-1-1 access rate ■ User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed write ■ Asynchronous output enable ■ CY7C1441KV33, CY7C1443KV33, and CY7C1441KVE33 are available in JEDEC-standard 100-pin TQFP and 165-ball FBGA Pb-free packages. ■ IEEE 1149.1 JTAG-Compatible Boundary Scan ■ “ZZ” Sleep Mode option ■ On-chip error correction code (ECC) to reduce soft error rate (SER) Functional Description The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 are 3.3 V, 1M × 36/2M × 18/1M × 36 synchronous flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock (CLK) input. The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 allow either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 operate from a +3.3 V core power supply while all outputs may operate with either a +2.5 V or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide Description 133 MHz Unit Maximum access time 6.5 ns Maximum operating current × 18 150 mA × 36 170 |
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