Document Number: 001-94722 Rev. *E

Page 20 of 29

CY7C1441KV25

Switching Characteristics

Over the Operating Range

Parameter [17, 18]

Description

-133

Unit

Min

Max

1

–

ms

Clock

Clock cycle time

7.5

–

ns

Clock HIGH

2.5

–

ns

Clock LOW

2.5

–

ns

Output Times

Data output valid after CLK rise

–

6.5

ns

Data output hold after CLK rise

2.5

–

ns

Clock to low Z [20, 21, 22]

2.5

–

ns

Clock to high Z [20, 21, 22]

–

3.8

ns

OE LOW to output valid

–

3.0

ns

OE LOW to output low Z [20, 21, 22]

0

–

ns

OE HIGH to output high Z [20, 21, 22]

–

3.0

ns

Setup Times

Address setup before CLK rise

1.5

–

ns

ADSP, ADSC setup before CLK rise

1.5

–

ns

ADV setup before CLK rise

1.5

–

ns

1.5

–

ns

Data input setup before CLK rise

1.5

–

ns

Chip enable setup

1.5

–

ns

Hold Times

Address hold after CLK rise

0.5

–

ns

ADSP, ADSC hold after CLK rise

0.5

–

ns

0.5

–

ns

ADV hold after CLK rise

0.5

–

ns

Data input hold after CLK rise

0.5

–

ns

Chip enable hold after CLK rise

0.5

–

ns

Notes

18. Test conditions shown in (a) of Figure 3 on page 19 unless otherwise noted.

be initiated.

bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve

High Z prior to Low Z under the same system conditions.

22. This parameter is sampled and not 100% tested.