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CY7C1441KV25 Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY7C1441KV25
Description  36-Mbit (1M36) Flow-Through SRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1441KV25 Datasheet(HTML) 5 Page - Cypress Semiconductor

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Document Number: 001-94722 Rev. *E
Page 5 of 29
CY7C1441KV25
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-Synchronous Address Inputs. Used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled
active. A[1:0] feed the 2-bit counter.
BWA, BWB, BWC,
BWD
Input-Synchronous Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
GW
Input-Synchronous Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes are written, regardless of the values on
BWX and BWE).
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW during a burst operation.
CE1
Input-Synchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1
is HIGH. CE1 is sampled only when a new external address is loaded.
CE2
Input-Synchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select or deselect the device. CE2 is sampled only
when a new external address is loaded.
CE3
Input-Synchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select or deselect the device. CE3 is sampled only
when a new external address is loaded.
OE
Input-Asynchronous Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
tri-stated and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
ADV
Input-Synchronous Advance Input Signal. Sampled on the rising edge of CLK. When asserted, it automat-
ically increments the address in a burst cycle.
ADSP
Input-Synchronous Address Strobe from Processor. Sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Input-Synchronous Address Strobe from Controller. Sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
BWE
Input-Synchronous Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
ZZ
Input-Asynchronous ZZ Sleep Input, Active HIGH. When asserted HIGH places the device in a non
time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin must be LOW or left floating. ZZ pin has an internal pull down.
DQs
I/O-Synchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The outputs
are automatically tri-stated during the data portion of a write sequence, during the first
clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
DQPX
I/O-Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs.
During write sequences, DQPx is controlled by BWX correspondingly.


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