CY7C1440KV33 datasheet(22/33 Pages) CYPRESS

Part #	CY7C1440KV33

Description	36-Mbit (1M 횞 36/2M 횞 18) Pipelined Sync SRAM (With ECC)

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Manufacturer	CYPRESS [Cypress Semiconductor]

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22 / 33 page

CY7C1440KV33

CY7C1442KV33

CY7C1440KVE33

Document Number: 001-66676 Rev. *G

Page 22 of 33

Capacitance

Parameter [19]

Description

Test Conditions

100-pin TQFP

Max

165-ballFBGA

Max

Unit

CIN

Input capacitance

TA = 25 C, f = 1 MHz,

VDD = 3.3 V, VDDQ = 2.5 V

5

pF

CCLK

Clock input capacitance

5

pF

CI/O

Input/output capacitance

5

pF

Thermal Resistance

Parameter [19]

Description

Test Conditions

100-pin TQFP

Package

165-ballFBGA

Package

Unit

JA

Thermal resistance

(junction to ambient)

Test

conditions

follow standard test

methods

and

procedures

for

measuring thermal

impedance,

per

EIA/JESD51.

With Still Air (0 m/s)

35.36

14.24

°C/W

With Air Flow (1 m/s)

31.30

12.47

°C/W

With Air Flow (3 m/s)

28.86

11.40

°C/W

JC

Thermal resistance

(junction to case)

–7.52

3.92

°C/W

JB

Thermal resistance

(junction to board)

28.89

7.19

°C/W

AC Test Loads and Waveforms

Figure 3. AC Test Loads and Waveforms

OUTPUT

R = 317



R = 351



5pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

RL = 50 

Z0 = 50 

VT= 1.5 V

3.3 V

ALL INPUT PULSES

VDDQ

GND

90%

10%

90%

10%

2 V/ns

 1ns

(c)

OUTPUT

R = 1667



R = 1538



5pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

RL = 50 

Z0 = 50 

VT = 1.25 V

2.5 V

ALL INPUT PULSES

VDDQ

GND

90%

10%

90%

10%

2 V/ns

 1ns

(c)

3.3 V I/O Test Load

2.5 V I/O Test Load

Note

19. Tested initially and after any design or process change that may affect these parameters.

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