CY7C1440KV33 datasheet(20/33 Pages) CYPRESS

Part #	CY7C1440KV33

Description	36-Mbit (1M 횞 36/2M 횞 18) Pipelined Sync SRAM (With ECC)

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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20 / 33 page

CY7C1440KV33

CY7C1442KV33

CY7C1440KVE33

Document Number: 001-66676 Rev. *G

Page 20 of 33

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. User guidelines are not tested.

Storage temperature ................................ –65 °C to +150 °C

Ambient temperature with

power applied .......................................... –55 °C to +125 °C

Supply voltage on VDD relative to GND .......–0.3 V to +4.6 V

Supply voltage on VDDQ relative to GND ...... –0.3 V to +VDD

DC voltage applied to outputs

in tri-state ..........................................–0.5 V to VDDQ + 0.5 V

DC input voltage ................................. –0.5 V to VDD + 0.5 V

Current into outputs (LOW) ........................................ 20 mA

Static discharge voltage

(per MIL-STD-883, method 3015) ......................... > 2001 V

Latch-up current ................................................... > 200 mA

Operating Range

Range

Ambient

Temperature

VDD

VDDQ

Commercial

0 °C to +70 °C

3.3 V

– 5% /

+ 10%

2.5 V – 5% to

VDD

Industrial

–40 °C to +85 °C

Neutron Soft Error Immunity

Parameter

Description

Test

Conditions Typ Max* Unit

LSBU (Device

without ECC)

Logical

Single-Bit

Upsets

25 °C

<5

5

FIT/

Mb

LSBU (Device

with ECC)

0

0.01 FIT/

Mb

LMBU (All

Devices)

Logical

Multi-Bit

Upsets

25 °C

0

0.01 FIT/

Mb

SEL (All

Devices)

Single Event

Latch up

85 °C

0

0.1

FIT/

Dev

* No LMBU or SEL events occurred during testing; this column represents a

statistical

2, 95% confidence limit calculation. For more details refer to Application

Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial

Failure Rates”.

Electrical Characteristics

Over the Operating Range

Parameter [17, 18]

Description

Test Conditions

Min

Max

Unit

VDD

Power supply voltage

–

3.135

3.6

V

VDDQ

I/O supply voltage

for 3.3 V I/O

3.135

VDD

V

for 2.5 V I/O

2.375

2.625

V

VOH

Output HIGH voltage

for 3.3 V I/O, IOH =4.0 mA

2.4

–

V

for 2.5 V I/O, IOH =1.0 mA

2.0

–

V

VOL

Output LOW voltage

for 3.3 V I/O, IOL = 8.0 mA

–

0.4

V

for 2.5 V I/O, IOL = 1.0 mA

–

0.4

V

VIH

Input HIGH voltage[17]

for 3.3 V I/O

2.0

VDD + 0.3 V

V

for 2.5 V I/O

1.7

VDD + 0.3 V

V

VIL

Input LOW voltage[17]

for 3.3 V I/O

–0.3

0.8

V

for 2.5 V I/O

–0.3

0.7

V

IX

Input leakage current except ZZ

and MODE

GND

 VI  VDDQ

–5

5

µA

Input current of MODE

Input = VSS

–30

–

µA

Input = VDD

–5

µA

Input current of ZZ

Input = VSS

–5

–

µA

Input = VDD

–30

µA

IOZ

Output leakage current

GND

 VI  VDDQ, output disabled

-5

5

µA

Notes

17. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).

18. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

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