CY7C1440KV33

CY7C1442KV33

CY7C1440KVE33

Document Number: 001-66676 Rev. *G

Page 18 of 33

Identification Register Definitions

Instruction Field

CY7C1440KV33 (1M × 36)

Description

Revision number (31:29)

000

Describes the version number.

Device depth (28:24)[14]

01011

Reserved for internal use.

Architecture/memory type (23:18)

000000

Defines memory type and architecture.

Bus width/density(17:12)

100111

Defines width and density.

Cypress JEDEC ID code (11:1)

00000110100

Allows unique identification of SRAM

vendor.

ID register presence indicator (0)

1

Indicates the presence of an ID register.

Scan Register Sizes

Register Name

Bit Size (× 36)

Instruction

3

Bypass

1

ID

32

Boundary scan order (165-ball FBGA package)

89

Identification Codes

Instruction

Code

Description

EXTEST

000

Captures the I/O ring contents.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operations.

SAMPLE Z

010

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces

all SRAM output drivers to a high Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

100

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does

not affect SRAM operation.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

RESERVED

110

Do Not Use: This instruction is reserved for future use.

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

Note

14. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.